Pass transistor logic circuit for reducing power consumption

Details Pass transistor logic circuit for reducing power consumption Pass transistor logic circuit for reducing power consumption

2000-09-25

2002-04-16

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S119000, C326S122000

Reexamination Certificate

active

06373291

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Application No. H11-273338 filed on Sep. 27, 1999 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, it relates to a pass-transistor logic circuit.
2. Related Background Art
One of approaches for reducing consumption power in large scale integrated circuit (LSI) is a pass-transistor logic circuit. Lee et al. in Kobe University compares logical units of pass-transistors configured with N-channel MOS transistors to logical units of pass-transistors configured with transmission gates (TG) in an article titled “Designs of Adders on NMOS and CMOS-TG Pass-transistor Logics and Comparative Evaluation”, DA Symposium '98. They conclude that “. . . as a result of comparison of NMOS with CMOS-TG, NMOS showed good delay performance on pass-input while CMOS-TG showed good delay performance on select input . . . ” in “Chap. 5: The Conclusions” of the article. In other words, they evaluate that it is desirable that NMOS pass-transistor logic may be used at locations where delay of signals acting as pass-input cause some trouble while CMOS-TG pass-transistor logic may be used at locations where the delay of signals acting as select input cause some trouble, and preferably, two types of logics may be used depending upon terms and locations in which they are to be appropriately used, respectively.
However, using those two types of cells results in the cells in circuit deign increasing in number and in the circuit design encountering a problem of conditional determination on individual use of the cells, and preferably, simply one type of cells are used.
SUMMARY OF THE INVENTION
The present invention is directed to overcoming the above mentioned disadvantages, and therefore, it is an object of the present invention to provide pass-transistor logic circuits that commonly have features of NMOS pass-transistor logic enabling pass-input signals to be transmitted faster and features of CMOS-TG pass-transistor logic enabling select input signals to be transmitted faster.
Semiconductor integrated circuit according to the present invention comprises a first MOS transistor of a first conductivity type receiving a select signal at its gate, a second MOS transistor of a second conductivity type in parallel connection with the first MOS transistor and receiving an inverted signal of the select signal at its gate, and third MOS transistors of the second conductivity type receiving the select signals at their respective gates, and the semiconductor integrated circuit is configured to satisfy the relation as expressed by an inequality, W
1
>W
2
, where W
1
and W
2
are gate widths of the first and second MOS transistors, respectively, thereby providing a pass-transistor logic circuit that enables output signal to alter quickly upon alteration of the select input signal, enables the output signal to alter quickly upon alteration of pass-input signals, and enables the logic circuit itself to be implemented in a reduced area compared with the prior art CMOS-TG pass-transistor logic circuit.
The semiconductor integrated circuit configured as mentioned above further comprises fourth MOS transistors of the first conductivity type in parallel connection with the third MOS transistors and receiving the inverted signals at its gate, and the semiconductor integrated circuit is configured to satisfy the relation as expressed by an inequality, W
3
>W
4
, where W
3
and W
4
are gate widths of the third and fourth MOS transistors, respectively, thereby attaining the similar effects to those as mentioned above in paths of pass-input signals.
The semiconductor integrated circuit configured as mentioned above may include an inverter for producing the inverted signals.
The inverter includes a fifth MOS transistor of the first conductivity type and a sixth MOS transistor of the second conductivity type which are connected in series with each other between a supply potential node and a ground potential node and receive the select signal at their respective gates, and the semiconductor integrated circuit is also configured to satisfy the relation as expressed by an inequality, (W
6
/L
6
)>2×(W
5
/L
5
), where W
5
and W
6
are gate widths of the fifth and sixth MOS transistors, respectively, while L
5
and L
6
are gate lengths thereof, respectively, thereby providing a pass-transistor logic circuit that enables output signal to alter more quickly upon alteration of the select input signal, enables the output signal to alter quickly upon alternation of the pass-input signals, and enables the logic circuit itself to be implemented in a reduced area compared with the prior art CMOS-TG pass-transistor logic circuit.
The configuration of the inverter as mentioned above enables the similar effects to be accomplished when it is applied to the NMOS pass-transistor logic circuit and to the CMOS-TG pass-transistor logic circuit comprising primary pass-input signal transmission elements of two N-channel MOS transistors.
Specifically, the semiconductor integrated circuit comprises a first MOS transistor of a first conductivity type receiving a select signal at its gate, an inverter having a second MOS transistor of the first conductivity type and a third MOS transistor of a second conductivity type that are in serial connection between a supply potential node and a ground potential node and that receive the select signal at their respective gates, to produce an inverted signal of the select signal, and a fourth MOS transistor of the first conductivity type that receives the inverted signal at its gates, and the semiconductor integrated circuit is configured to satisfy the relation as expressed by an inequality, (W
3
/L
3
)>2×(W
2
/L
2
), where W
2
and W
3
are gate widths of the second and third MOS transistors, respectively, while L
2
and L
3
are gate lengths thereof, respectively, thereby enabling the similar effects to those as mentioned above to be accomplished.


REFERENCES:
patent: 4541067 (1985-09-01), Whitaker
patent: 5568069 (1996-10-01), Chow
patent: 5808483 (1998-09-01), Sako
patent: 5923189 (1999-07-01), Sasaki et al.
patent: 5955912 (1999-09-01), Ko
Lee et al., “32-Bit Adder Design and Comparison with NMOS/CMOS-TG Pass-Transistor Logic,” DA Symposium (1998), pp. 65-70.

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