Pass transistor circuit with exclusive controls

Details Pass transistor circuit with exclusive controls Pass transistor circuit with exclusive controls

2000-12-01

2004-04-13

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S114000, C716S030000

Reexamination Certificate

active

06720797

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a pass transistor circuit used as a selector employing pass transistors, a pass transistor circuit design method, a logic circuit optimization device used to optimize buffering in designing a logic circuit, a logic circuit optimization method and a computer-readable recording medium in which a computer program which when executed on a computer realizes the method according to the present invention.
BACKGROUND OF THE INVENTION
In the recent semiconductor LSI (Large Scale Integrated Circuit) field, a method for designing a logic circuit using pass transistors has been widely utilized. Especially, A logic circuit composition method using a binary decision diagram plays a significant role in separating a logic circuit into select logics and putting the design of a logic circuit using pass transistors to practical use. In addition, it is known that in a pass transistor logic circuit, the number of normally used transistors is smaller than the number of CMOS (Complementary Metal Oxide Semiconductor) gates, thereby facilitating realizing low power consumption and high integration.
On the other hand, potential problems with the use of a pass transistor include that the pass transistor lacks in a force for driving other transistors such as a CMOS circuit. Due to this, conventionally, a plurality of stages of pass transistors are connected to thereby cause waveform deformation of an electric signal, thus rather sacrificing timing performance. In these circumstances, demand for providing means and a method capable of overcoming these disadvantages more effectively than before rises.
Recently, with the progress of the high integration of a semiconductor integrated circuit, attention is increasingly paid to a pass transistor capable of realizing high integration with low power consumption. A technique of this type has been frequently used in designing mainly a memory or a programmable logic array. Since the design of a logic circuit employing a binary decision diagram theory was published, this technique has been employed positively with a view to higher integration, lower power consumption and higher speed.
The binary decision diagram theory is a theory for realizing logic circuit design in which a logic function is translated to an appropriate binary tree by using the binary decision diagram and the resultant tree is replaced by a pass transistor selector having a pair of exclusive select inputs and one output. Conventionally, logic composition and circuit optimization are carried out based on the binary decision diagram theory.
For example, Japanese Patent Application Laid-Open No. 9-6821 (to be referred to as “Publication 1” hereinafter) discloses a method of efficiently probing a binary decision diagram. According to this method, temporary circuits of AND and OR circuits are composed from a logic function and grouped based on the input correlation, and the binary decision graph is probed while optimizing a combination of groups to thereby replace the circuits by a pass transistor selector.
Meanwhile, it has become conventionally possible to easily create a logic by applying pass transistors to a logic circuit. Although effective in solving a select logic, the pass transistor has an essential disadvantage in that a signal driving force should be supplied from another CMOS gate. This disadvantage is, therefore, one factor which makes circuit design difficult.
Further, in designing logic, if a circuit logically composed using a pass transistor cannot be actually used due to the occurrence of a waveform deformation, it is necessary to change circuit arrangement. To do so, a method for intentionally mixing an optimal combination of CMOS logics into a logic circuit including pass transistors, is adopted.
Japanese Patent Application Laid-Open No. 9-321146 (to be referred to as “Publication 2” hereinafter) and Japanese Patent Application Laid-Open No. 10-200394 (to be referred to as “Publication 3” hereinafter) disclose the above-stated method as well as a method for optimizing a circuit area, delay time and power consumption. Namely, Publication 2 discloses a method including registering both logically equivalent CMOS circuit and pass transistor circuit cells in a library and combining them according to required conditions so as to allow the mixture of the CMOS logic and the pass transistor logic and to automatically optimize the circuit area, delay time and power consumption.
Publication 3 discloses a method including replacing portions having inputs fixed to “0” and “1” of a pass transistor type logic circuit created based on the binary decision diagram theory by NAND and NOR circuits of a logically equivalent CMOS circuits and adjusting the circuits in light of the performance and required values of the overall circuits.
As disclosed by Publications 2 and 3, it is conventionally impossible to satisfy required performance only with the pass transistor logic and the CMOS logic is, therefore, still employed to the ordinary design of logic. Nevertheless, the pass transistors are often used only for a pass transistor selector circuit capable of making most use of the features of the CMOS theory.
FIG. 23A
shows a design example 1 of a conventional logic circuit (or the pass transistor selector circuit in this case). The pass transistor selector circuit shown therein consists of n NMOS pass transistors t
0
to tn provided at an input side and an inverter inv
0
and a voltage holding PMOS transistor pt
0
provided at an output side. Input signals s
0
to sn are inputted into the input terminals i
0
to in of these pass transistors t
0
to tn, respectively. In addition, the continuities of the pass transistors t
0
to tn are controlled by control signals se
10
to se
1
n inputted into gates g
0
to gn, respectively. Here, the level of only one of the control signals se
10
to se
1
n is H (active) and the levels of the remaining control signals are L.
The drains d
0
to dn of the pass transistors t
0
to tn, respectively, are connected to the input terminal of the inverter inv
0
. The inverter inv
0
inverts the output signal of any one of the pass transistors t
0
to tn and outputs the inverted signal as an output signal o
0
. This inverter inv
0
exists at a node n
0
. The voltage holding PMOS transistor pt
0
is intended to hold voltage. The drain dp of the voltage holding PMOS transistor pt
0
is connected to the input terminal of the inverter inv
0
and the gate gp thereof is connected to the output terminal of the inverter inv
0
.
If the level of the control signal se
10
is set at H and those of the other control signals se
1
to seln are set at L, then only the pass transistor t
0
becomes continuous and an input signal s
0
is thereby selected from among the input signals s
0
to sn. As a result, the input signal s
0
is inverted by the inverter inv
0
and then outputted as an output signal o
0
.
Additionally, a pass transistor selector circuit shown in
FIG. 23B
is conventionally used. In
FIG. 23B
, a selector function is realized by employing complementary transfer gates C
0
to Cn instead of the pass transistors t
0
to tn shown in FIG.
23
A. It is noted that the pass transistor selector circuit shown in
FIG. 23B
is not provided with a voltage holding PMOS transistor pt
0
and in this case (like shown in FIG.
23
B), any CMOS gate (AND, OR, etc. . .) can be switched instead of inverter inv
0
(Not shown).
In the meantime, as already stated above, the conventional design has disadvantage in that the load capacity of the pass transistor selector circuit dynamically changes according to the values of the control signals se
10
to se
1
n shown in FIG.
23
A. Namely, if the level of the control signal se
10
is H and the levels of the control signals sel
1
, sel
2
, . . . and seln are L, then a load capacity Ct to be driven from the input terminal i
0
becomes the sum of parasitic capacities Cs
0
and Cd
0
at the source and drain d
0
of the pass transistor t
0
through which the input signal s
0
passes, a gate capacity Cinv
0

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