Pass transistor circuit

Details Pass transistor circuit Pass transistor circuit

1998-12-22

2001-04-17

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S027000

Reexamination Certificate

active

06218867

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pass transistor circuits, which includes a plurality of pass transistor sections. More particularly, the present invention relates to a pass transistor circuit produced by a CMOSFET (Complementary Metal-Oxide-Semiconductor Field-Effect Transistor) process utilizing a TFT (Thin Film Transistor) technique.
2. Description of the Related Art
Conventionally, in order to reduce the number of transistors used, a pass transistor circuit is implemented with pass logic sections (pass gates) each formed of either an n-type (n-channel) MOSFET or a p-type (p-channel) MOSFET.
FIGS. 5 and 6
illustrate such a conventional pass transistor circuit. As illustrated in the figures, the pass gate section of the pass transistor circuit includes four transistors Tr
1
to Tr
4
, which are all n-type MOSFETs.
FIG. 7
illustrates another conventional pass transistor circuit. This pass transistor circuit is called a “CVSL (Cascode Voltage Swing Logic)” circuit developed by IBM corporation, where the pass gate sections of the pass transistor circuit are each formed only of an n-type MOSFET.
FIG. 8
illustrates still another conventional pass transistor circuit. This pass transistor circuit is called a “DPL (Double Pass-transistor Logic” developed by Hitachi Ltd, where the pass gate sections of the pass transistor circuit are each formed only of an n-type MOSFET.
The pass transistor circuit diagrams illustrated in
FIGS. 5
to
8
are from “White paper on low power consumption LSIs”, Nikkei Business Publications Inc.
Other conventional pass transistor circuits include those described in Japanese Laid-open Publication Nos. 8-321770 and 9-93118.
In the pass transistor circuit described in Japanese Laid-open Publication No. 8-321770, the pass gate section is formed only of either an n-type transistor or a p-type transistor.
The pass transistor circuit employs an output-latch-type circuit configuration, in which the output is fully swung, but the pass gate section is again formed only of a single transistor.
As described above, in the conventional pass transistor circuit, the pass gate section is formed only of either an n-type transistor or a p-type transistor.
Referring to
FIGS. 6 and 9
, a problem associated with such a conventional pass transistor circuit, where the pass gate section is formed only of an n-type MOSFET, will be described.
FIG. 9
is a layout diagram illustrating a structure corresponding to that illustrated in
FIGS. 5 and 6
, with the pass transistor circuit sections being replaced by transistor circuits.
Consider a case where input signals A and B to the pass gate sections are each at a high level, and the n-type transistors Tr
2
and Tr
4
are both turned ON. When an input signal C is at a low level, an inverted signal C bar (inverted from the signal C) is first transmitted to a node N#
1
.
However, since the transistors Tr
2
and Tr
4
are both n-type MOSFETs, the high level signal which equals V
DD
, the positive power supply voltage) is not transmitted therethrough. Therefore, the node N#
1
is only charged up to V
DD
−Vthn (where Vthn denotes a threshold voltage of the n-type MOSFET).
Thus, if the circuit of
FIG. 6
does not have transistors Tr
5
, Tr
8
and Tr
9
, a transistor Tr
6
is not completely turned OFF, thereby causing a DC current between the transistor Tr
6
and a transistor Tr
7
.
Conventionally, in order to solve this problem, the n-type MOSFET transistors Tr
5
, Tr
8
and Tr
9
are provided as auxiliary circuits, as illustrated in FIG.
6
.
In this configuration with the auxiliary circuits, as illustrated in
FIG. 6
, when the node N#
1
is initially (i.e.) before the signal C bar (at the high level) is inverted from input signal C and transmitted thereto) set to a low level (equal to GND, or ground level), the transistors Tr
6
and Tr
8
are ON. When the signal C bar is transmitted therethrough, the transistors Tr
7
and Tr
9
are then turned ON, a node N#
2
is at a low level, and the transistor Tr
5
is turned ON. Thus, the node N#
1
is charged from V
DD
−Vthn to V
DD
.
When the signal to be transmitted is at the low level, and the node N#
1
is initially at the high level, a DC current is generated from the transistor Tr
5
toward the signal to be transmitted, and the transistor Tr
8
is turned ON by the potential at the node N#
1
, thereby bringing the node N#
2
to the high level. The DC current keeps flowing until the transistor Tr
5
is turned OFF. Thus, as the potential at the node N#
1
changes from the high level to the low level, the transistor Tr
5
and the signal source (low level) collide with each other, thereby generating a DC current flowing from Tr
5
→Tr
4
→Tr
2
→C bar (which is equal to a low level).
As described above, when only the n-type MOSFET is used for the pass gate, due to the characteristics of the n-type transistor, only the signal amplitude “V
DD
-Vthn” of a high level signal is transmitted therethrough.
When only the p-type characteristics MOSFET is used for the pass gate, due to the characteristics of the p-type transistor, only the signal amplitude “GND+¦Vthp¦” of a low level signal is transmitted therethrough (where Vthp denotes the threshold voltage of the p-type MOSFET).
In order to solve these problems, conventionally, the above-described auxiliary circuits are additionally provided. In such a configuration, however, a temporary or steady DC current occurs in the auxiliary circuits.
This results from the formation of the pass gate using only an n-type MOSFET or a p-type MOSFET.
SUMMARY OF THE INVENTION
According to one aspect of this invention, a pass transistor circuit includes a plurality of pass transistor sections having pass transistor logics and has a logic functionality of a plurality of pass transistor sections. One or more of the pass transistor sections is a CMOSFET formed of a p-type MOSFET and an n-type MOSFET. At least one of the p-type MOSFET and the n-type MOSFET of the CMOSFET is a transistor having a TFT structure.
In one embodiment of the invention, one of the pass transistor sections is formed only of an n-type MOSFET whose source is connected to GND.
In one embodiment of the invention, one of the pass transistor sections is formed only of a p-type MOSFET whose source is connected to a positive power source V
DD
.
In one embodiment of the invention, both of the p-type MOSFET and the n-type MOSFET of the CMOSFET are transistors having a TFT structure.
In one embodiment of the invention, one of the pass transistor sections is formed only of a p-type MOSFET whose source is connected to a positive power source V
DD
.
Functions of the present invention will now be described.
As described above, in the pass transistor circuit of the present invention, some or all of a plurality of pass transistor sections are CMOSFETs each including an n-type MOSFET and a p-type MOSFET. Thus, for reasons set forth below, the auxiliary circuits (Tr
5
, Tr
8
and Tr
9
) illustrated in
FIGS. 5 and 6
, which are required in the conventional pass transistor circuit, are not necessary, thereby eliminating a through current caused by the auxiliary circuits.
In the conventional pass transistor circuit where each pass transistor section is formed only of an n-type MOSFET, a high level signal passes through the gate with the potential thereof being V
DD
−Vthn. According to the present invention, a p-type transistor is additionally provided along with the n-type MOSFET, thereby transmitting the high level signal with the potential thereof being V
DD
.
In the conventional pass transistor circuit where each pass transistor section is formed only of a p-type MOSFET, a low level signal passes through the gate with the potential thereof being GND+¦Vthp¦. According to the present invention, an n-type transistor is additionally provided along with the p-type MOSFET, thereby transmitting the low level signal with the potential thereof being GND.
Therefore, according to the present i

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