Partitioning a large design across multiple devices

Details Partitioning a large design across multiple devices Partitioning a large design across multiple devices

2011-01-18

2011-01-18

Levin, Naum B (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07873927

ABSTRACT:
A method of partitioning a design across a plurality of integrated circuits can include creating a software construct for each one of the plurality of integrated circuits and assigning a plurality of instances to a selected software construct. Each of the plurality of instances can be from a different logic hierarchy. The method further can include automatically adding at least one input/output buffer and port to the selected software construct to accommodate the plurality of instances and creating nets connecting the plurality of instances and the at least one input/output buffer and port within the selected software construct.

REFERENCES:
patent: 4918614 (1990-04-01), Modarres et al.
patent: 5140526 (1992-08-01), McDermoth et al.
patent: 5452228 (1995-09-01), Arakawa et al.
patent: 5452239 (1995-09-01), Dai et al.
patent: 5461576 (1995-10-01), Tsay et al.
patent: 5499191 (1996-03-01), Young
patent: 5499192 (1996-03-01), Knapp et al.
patent: 5513119 (1996-04-01), Moore et al.
patent: 5596742 (1997-01-01), Agarwal et al.
patent: 5617327 (1997-04-01), Duncan
patent: 5634050 (1997-05-01), Krueger et al.
patent: 5648913 (1997-07-01), Bennett et al.
patent: 5659484 (1997-08-01), Bennett et al.
patent: 5696693 (1997-12-01), Aubel et al.
patent: 5784290 (1998-07-01), Kung et al.
patent: 5991523 (1999-11-01), Williams et al.
patent: 6009251 (1999-12-01), Ho et al.
patent: 6045252 (2000-04-01), Pedersen
patent: 6145117 (2000-11-01), Eng
patent: 6170080 (2001-01-01), Ginetti et al.
patent: 6189131 (2001-02-01), Graef et al.
patent: 6223329 (2001-04-01), Ling et al.
patent: 6249903 (2001-06-01), McSherry et al.
patent: 6317863 (2001-11-01), Segal
patent: 6408422 (2002-06-01), Hwang et al.
patent: 6467074 (2002-10-01), Katsioulas et al.
patent: 6487708 (2002-11-01), Canaris
patent: 6505323 (2003-01-01), Lipton et al.
patent: 6530070 (2003-03-01), Kruse
patent: 6618834 (2003-09-01), Takeyama et al.
patent: 6622291 (2003-09-01), Ginetti
patent: 6631508 (2003-10-01), Williams
patent: 6684376 (2004-01-01), Kerzman et al.
patent: 6711729 (2004-03-01), McElvain et al.
patent: 6817005 (2004-11-01), Mason et al.
patent: 6845494 (2005-01-01), Burks et al.
patent: 7013438 (2006-03-01), Saldanha et al.
patent: 7073149 (2006-07-01), Knol et al.
patent: 7103863 (2006-09-01), Riepe et al.
patent: 7117473 (2006-10-01), Knol et al.
patent: 7120892 (2006-10-01), Knol et al.
patent: 7146595 (2006-12-01), Knol et al.
patent: 7168041 (2007-01-01), Durrill et al.
patent: 7188327 (2007-03-01), Hahn
patent: 7370302 (2008-05-01), Knol et al.
patent: 2002/0124230 (2002-09-01), Cai et al.
patent: 2004/0078767 (2004-04-01), Burks et al.
patent: 2005/0268269 (2005-12-01), Coiley
U.S. Appl. No. 11/099,887, filed Apr. 5, 2005, Knol, David A. et al., entitled “Partitioning a Large Design Across Multiple Devices”, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Aplpl. No. 11/100,290, Ranjan et al., filed Apr. 5, 2005,entitled “Method of Memory and Run-Time Efficient Hierarchical Timing Analysis in Programmable Logic Devices”, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 11/152,502, Knol et al., filed Jun. 14, 2005, entitled “System for Representing the Logical and Physical Information of an Integrated Circuit”, 68 pgs., Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
Cong et al., “Buffer block planning for interconnected-driven floorplanning”, Computer-Aided Design, 1999, Digest of Technical Papers, 1999 IEEE/ACM International Conference on Nov. 7-11, 1999, pp. 358-363.
Hiwatashi, T. et al., “An interactive/automatic floor planner for hierarchically designed cell bases VLSIs”, Custom Integrated Circuits Conference, 1990, Proceedings of the IEEE 1990., May 13-16, 1990, pp. 30.4/1-30.4/4.
Ranjan et al., “Fast hierarchical floorplanning with congestion and timing control”, Computer Design, 2000, Proceedings 2000 International Conference Sep. 17-20, 2000, pp. 357-362.
Sarkar et al., “Routability-driven repeater block planning for interconnect-centric floorplanning”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on vol. 20, Issue 5, May 2001, pp. 660-671.
Wang, Maogang, et al., “Multi-Million Gate FPGA Physical Design Challenges”, ICCAD, Nov. 1003, pp. 891-898, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.

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