Partitioned random access memory

Details Partitioned random access memory Partitioned random access memory

2005-02-08

2005-02-08

Chase, Shelly A (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

06854084

ABSTRACT:
A random access memory includes a first memory bank, a second memory bank, an error checking circuit operatively connected to receive data read from the first memory bank, and a multiplexer operatively connected to input data read from both the first memory bank and the second memory bank, wherein input selection of the multiplexer is controlled by an output of the error checking circuit. A method for reducing errors in a memory system includes writing data into first and second memory banks of the memory system in parallel, reading data from a desired location of the first memory bank, checking the data read from the first memory bank for errors, if no errors are present, outputting the data read from the first memory bank to a bus, and if the data read from the first memory bank contains errors, outputting data read from a parallel location in the second memory bank to the bus. A method for reducing errors in a memory system comprises writing data into first and second memory banks of the memory system in parallel, reading data from a desired location of the first memory bank, checking the data read from the first memory bank for errors, if no errors are present, outputting the data read from the first memory bank to a bus, and if the data read from the first memory bank contains errors, outputting data read from a parallel location in the second memory bank to the bus.

REFERENCES:
patent: 5611042 (1997-03-01), Lordi
patent: 5916314 (1999-06-01), Berg et al.
patent: 6237124 (2001-05-01), Plants
International Search Report, dated May 28, 2002 (7 pages).
700 IBM Technical Disclosure Bulletin, vol. 31, No. 3, Aug. 1988, Armonk, NY (4 pages).
P.R. Turgeon, et al., “Two Approaches to Array Fault Tolerance in the IBM Enterprise System/9000 Type 9121 Processor”, IBM Journal of Research and Development, vol. 35, No. 3, May 1991, Armonk, NY (7 pages).

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