Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-01-30
2004-03-02
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S030000
Reexamination Certificate
active
06701457
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to computers, and more particularly relates to partitioned computers, and even more particularly relates to methods and systems for debugging partitioned avionics computers.
BACKGROUND OF THE INVENTION
In recent years, partitioned computers have become increasingly prevalent in many industries. One example is the aviation electronics community where cockpit integration has progressed so extensively that what was once a collection of numerous independent hardware black boxes is now a single partitioned avionics computer which hosts independent proprietary avionics software programs produced by competing avionics companies. In the avionics industry, it is also often necessary to service such equipment in a very rapid manner. If such avionics equipment requires such extensive service that the aircraft is even temporarily taken out of revenue service, the financial impact on the airline can be substantial. Consequently, it is desirable to have a system and method for debugging such software systems in an efficient manner, which also does not require disclosure of the contents of one avionics company's proprietary software to its competitor.
One prior art approach to this situation has been to interrupt the normal functioning of the system processor by capturing the processor and using it to examine and debug the various partitioned memory sections of the computer.
While this approach has been used extensively in the past, it does have obvious drawbacks. For example, capturing and using the system processor until the debugging operation is complete can be quite time consuming and, therefore, disruptive to the normal operation of the computer.
Consequently, there exists a need for improved methods and systems for debugging partitioned avionics computers in an efficient manner.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a system and method for debugging a computer in an efficient manner.
It is a feature of the present invention to utilize an independent debugging dump memory and debugging dump memory controller.
It is another feature of the present invention to dedicate a predetermined amount of processor time of the primary processor in the host operating system to memory transfer for debugging purposes.
It is an advantage of the present invention to permit debugging of computers without requiring the main system microprocessor to perform debugging operations.
It is another advantage of the present invention to permit debugging without compromising safety or guaranteed performance.
It is another advantage of the present invention to permit debugging of computers with installed software, which has received an official review and response from an official of a governmental agency which regulates air safety, while such computers and software are in use for revenue service.
The present invention is an apparatus and method for debugging computers designed to satisfy the aforementioned needs, provide the previously stated objects, include the above-listed features, and achieve the already articulated advantages. The present invention is carried out in an “interference-less” manner in a sense that the interference in the normal operation of a host computer during debugging operations has been greatly reduced and that such interference is known a priori.
Accordingly, the present invention is a system and method including a computer having an independent debugging dump memory and a debugging dump memory controller, which takes control of the memory access bus for a predetermined amount of time on a predefined schedule. The debug controller and other mechanisms of the present invention may be implemented as separate physical components, or included within the physical design and implementation of a single physical device.
Control may be returned to the main system by either of two means: Preemption of the debug mechanism by the main processor at the completion of a predefined time interval, or by release of main system resources by the debug system at the completion of the memory transfer.
The present invention has utility for initial development testing, hardware/software integration and testing, requirements verification and validation, as well as other testing either prior to or following official review and response from an official of a governmental agency who regulates air safety (commonly called appliance approval).
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Fannin Timothy R.
Reynolds Brian A.
Baderman Scott
Eppele Kyle
Jensen Nathan O.
Lohn Joshua A
Rockwell Collins
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