Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-06-08
2001-06-19
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S358000, C257S359000, C257S059000, C257S299000
Reexamination Certificate
active
06249027
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and in particular, the present invention relates to partially depleted silicon-on-insulator (SOI) devices which include a mechanism for tuning the threshold voltage thereof.
2. Description of the Related Art
The partially depleted SOI device is a MOS transistor formed in a monocrystalline silicon substrate sitting above an insulating oxide layer, called a back oxide. The source/drain regions usually penetrate down to the back oxide. The channel region between the source and drain is doped so that the depletion region under the gate does not extend to the back oxide. This is the important difference between partially depleted and fully depleted SOI devices.
Silicon-on-insulator (SOI) devices are thus characterized by structures in which the Si device layers are formed over an insulating film.
FIG. 1
illustrates an exemplary configuration of such a device.
The device of
FIG. 1
includes an nfet
102
and a pfet
104
formed within a layer
106
. The layer
106
is located along an oxide layer
108
formed atop a p+ bulk material
110
. The nfet
102
includes source and drain n-regions
112
and
114
, a p-region
116
, and a gate electrode
118
. Likewise, the pfet
104
includes source and drain p-regions
120
and
122
, an n-region
124
, and a gate electrode
126
. SOI devices of this type are characterized by low parasitic capacitances, as well as high dielectric isolation of the on-chip components.
A “fully depleted” SOI device is shown in FIG.
2
. Here, the device is configured such that the depletion regions
228
extend completely down to the interface with the oxide layer
208
. This is done, for example, by making the layer
206
much thinner than the corresponding layer
306
of the partially depleted device shown in FIG.
3
and discussed below. The structure is otherwise similar to that of the partially depleted device, and includes an nfet
202
having source and drain n-regions
212
and
214
, a p-type channel region
216
, and a gate
218
, and a pfet
204
having source and drain p-regions
220
and
222
, an n-type channel region
224
, and a gate
226
. The substrate
210
is tied to a fixed potential such as ground.
A “partially depleted” SOI device refers to a structure in which the depletion region of the transistors does not extend all the way down to the oxide layer. An example of this is shown in FIG.
3
. Here, the layer
306
is of sufficient thickness and the n-regions
312
and
314
are appropriately configured (e.g., through use of source-drain extensions) such that the depletion region
328
is spaced from the upper surface of the oxide layer
308
, i.e., only a portion of the p-region
316
is depleted.
The non-depleted region between the source
312
and drain
314
is called the body or bulk. In conventional partially depleted SOI, the body is left floating or is connected to the source of the transistor. In another alternative, known as dynamic threshold MOS (DTMOS), the body is connected to the gate. This causes the threshold to be higher when the device is off than when it is on, which decreases the off-state leakage and increases the on-state current. Referring again to
FIG. 3
, a body contact
330
is embedded in the p-region
316
, below the depletion region
328
. Also, as shown, the body contact
330
is electrically tied to the gate electrode
318
. As such, when the gate potential is turned on, the potential of the p-region
316
below the depletion region
328
(i.e., the “bulk region”) is pulled up, whereby the bulk potential of the device tracks the gate potential. This results in a forward biasing of the bulk which in turn decreases the threshold voltage of the device.
There are a number of factors which contribute to the magnitude of an SOI device's threshold voltage. For example, to set a device's threshold voltage near zero, light doping and/or counter doping in the channel region of the device may be provided. However, due to processing variations, the exact dopant concentration in the channel region can vary slightly from device to device. Although these variations may be slight, they can shift a device's threshold voltage by a few tens or even hundreds of a millivolt. Further, dimensional variations, charge trapping in the materials and interfaces, and environmental factors such as operating temperature fluctuations can shift the threshold voltage. Still further, low threshold devices may leak too much when their circuits are in a sleep or standby mode. Thus, particularly for low-threshold devices, it is desirable to provide a mechanism for tuning the threshold voltage to account for these and other variations.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a partially depleted SOI device which includes a mechanism for tuning the threshold voltage of the device to account for variations in process, temperature and circuit activity.
To achieve the above and other objects and advantages, according to one aspect of the present invention, a semiconductor device includes a partially depleted SOI device which includes a semiconductor substrate, an insulating layer formed along a surface of the semiconductor substrate, and a transistor formed on the insulating layer such that the insulating layer is interposed between the transistor and the semiconductor substrate. The transistor includes source and drain regions of a first conductivity type formed on the insulating layer, an intermediate region of a second conductivity type formed on the insulating layer and between the source and drain regions, and a gate electrode aligned over the intermediate region. The intermediate region includes a depletion region defining a channel of the transistor and a non-depletion region defining a bulk of the transistor. First, second, third and fourth terminals are electrically coupled to the source region, drain region, gate electrode and bulk, respectively. The semiconductor device further includes a bias voltage generator having a bias voltage output which is coupled to the fourth terminal and isolated from the first through third terminals.
According to another aspect of the invention, the semiconductor device further includes a conductive body contact embedded in the bulk and connected to the fourth terminal.
According to still another aspect of the invention, the semiconductor device further includes a conductive layer of the second conductivity type contained within the bulk and connected to the fourth terminal.
According to yet another aspect of the invention, the bias voltage generator may be located off-chip.
REFERENCES:
patent: 4062699 (1977-12-01), Armstrong
patent: 4173818 (1979-11-01), Bassous et al.
patent: 4208780 (1980-06-01), Richman
patent: 4939571 (1990-07-01), Nishizawa et al.
patent: 4949140 (1990-08-01), Tam
patent: 5031008 (1991-07-01), Yoshida
patent: 5294821 (1994-03-01), Iwamatsu
patent: 5359219 (1994-10-01), Hwang
patent: 5429958 (1995-07-01), Matlock
patent: 5486480 (1996-01-01), Chen
patent: 5536959 (1996-07-01), Kellam
patent: 5557231 (1996-09-01), Yamaguchi et al.
patent: 5559368 (1996-09-01), Hu et al.
patent: 5565377 (1996-10-01), Weiner et al.
patent: 5605855 (1997-02-01), Chang et al.
patent: 5616944 (1997-04-01), Mizutani et al.
patent: 5641980 (1997-06-01), Yamaguchi et al.
patent: 5650340 (1997-07-01), Burr et al.
patent: 5712501 (1998-01-01), Davies et al.
patent: 5744994 (1998-04-01), Williams
patent: 5753958 (1998-05-01), Burr et al.
patent: 5773863 (1998-06-01), Burr et al.
patent: 5811857 (1998-09-01), Assaderaghi et al.
patent: 5854561 (1998-12-01), Arimoto et al.
patent: 5923067 (1999-07-01), Voldman
Minimization of Threshold Voltage Variation in SOI Mosfets, Sherony et al9, 1994.
Abraham Fetsum
Gunnison McKay & Hodgson, L.L.P.
McKay Philip J.
Sun Microsystems Inc.
LandOfFree
Partially depleted SOI device having a dedicated single body... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Partially depleted SOI device having a dedicated single body..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Partially depleted SOI device having a dedicated single body... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2467628