Partial way hint line replacement algorithm for a snoop filter

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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Reexamination Certificate

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07962694

ABSTRACT:
In an embodiment, a method is provided. The method of this embodiment provides receiving a request for data from a processor of a plurality of processors, determining a cache entry location based, at least in part, on the request, storing the data in a cache corresponding to the processor at the cache entry location, and storing a coherency record corresponding to the data in a snoop filter in accordance with one of the following, if there is a cache miss: at the cache entry location of a corresponding affinity in the snoop filter if the cache entry location is found in the corresponding affinity, or at a derived cache entry location of the corresponding affinity if the cache entry location is not found in the corresponding affinity.

REFERENCES:
patent: 6636946 (2003-10-01), Jeddeloh
patent: 6959364 (2005-10-01), Safranek et al.
patent: 6976129 (2005-12-01), Creta et al.
patent: 2006/0004963 (2006-01-01), Mattina et al.
patent: 2006/0053257 (2006-03-01), Sistla et al.
Kai Cheng et al., “Way Hint Line Replacement Algorith for a Snoop Filter”, U.S. Appl. No. 11/395,123, filed Mar. 31, 2006.
Sundaram Chinthamani et al., “Line Swapping Scheme to Reduce Back Invalidations in a Snoop Filter”, Appl #: TBD, Filed: Dec. 14, 2006.

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