Partial underfill for flip-chip electronic packages

Details Partial underfill for flip-chip electronic packages Partial underfill for flip-chip electronic packages

2000-10-23

2002-04-02

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Encapsulating

C438S108000, C438S118000, C438S126000

Reexamination Certificate

active

06365441

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an underfill for a C4 integrated circuit package.
2. Background Information
Integrated circuits are typically assembled into packages that are mounted to a printed circuit board. The package may include a substrate that has solder balls or other types of contacts that are attached to the circuit board. An integrated circuit is mounted to the substrate. The substrate typically has routing traces, vias, etc. that electrically connect the integrated circuit to the solder balls.
The integrated circuit may be connected to corresponding surface pads of the substrate with solder bumps in a process commonly referred to as controlled collapsed chip connection (C4). The substrate coefficient of thermal expansion is different than the coefficient of thermal expansion for the integrated circuit. When the package is thermally cycled the difference in thermal expansion may create a mechanical strain in the solder bumps. It has been found that the strain may create cracks and corresponding electrical opens in the solder bumps, particularly after a number of thermal cycles.
Most C4 packages contain an underfill material that is formed between the integrated circuit and the substrate. The underfill material structurally reinforces the solder bumps and improves the life and reliability of the package. The underfill material is typically dispensed onto the substrate in a liquid or semi-liquid form. The liquid underfill then flows between the integrated circuit and the substrate under a capillary action. The liquid underfill is eventually cured into a solid state.
The underfill process completely fills the space between the integrated circuit and the substrate to structurally reinforce all of the solder bumps. A number of techniques have been developed to insure that the underfill material surrounds all of the solder bumps. It is desirable to fill the space between the integrated circuit and the substrate to insure that gases are not trapped within the substrate/integrated circuit interface. The gases may escape during subsequent process steps, particularly if the package is heated and re-flowed onto a motherboard. The release of gases may cause a delamination of the package.
SUMMARY OF THE INVENTION
One embodiment of the present invention is an integrated circuit package that contains an underfill material. The underfill material may extend from an outer edge of the integrated circuit towards the center of the integrated circuit a length L
1
that is no less than approximately 25% of a length L
2
between the edges and a center of the integrated circuit.


REFERENCES:
patent: 4322737 (1982-03-01), Sliwa, Jr.
patent: 5321583 (1994-06-01), McMahon
patent: 5751556 (1998-05-01), Butler et al.
patent: 5766982 (1998-06-01), Akram et al.
patent: 5804771 (1998-09-01), McMahon et al.
patent: 5815372 (1998-09-01), Gallas
patent: 5891753 (1999-04-01), Akram
patent: 5917702 (1999-06-01), Barrow
patent: 5919329 (1999-07-01), Banks et al.
patent: 5920120 (1999-07-01), Webb et al.
patent: 5936304 (1999-08-01), Lii et al.
patent: 5953814 (1999-09-01), Sozansky et al.
patent: 5959362 (1999-09-01), Yoshino
patent: 5965937 (1999-10-01), Chiu et al.
patent: 5973930 (1999-10-01), Ikeda et al.
patent: 5981313 (1999-11-01), Tanaka
patent: 5990546 (1999-11-01), Igarashi et al.
patent: 5991161 (1999-11-01), Samaras et al.
patent: 5998242 (1999-12-01), Kirkpatrick et al.
patent: 6011301 (2000-01-01), Chiu
patent: 6016006 (2000-01-01), Kolman et al.
patent: 6049122 (2000-04-01), Yoneda
patent: 6093972 (2000-07-01), Carney et al.
patent: 6201301 (2001-03-01), Hoang
patent: 6252308 (2001-06-01), Akram et al.
patent: 0340492 (1989-04-01), None
patent: 0778616 (1996-11-01), None
patent: 3-040458 (1991-02-01), None

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