Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
2000-03-07
2003-06-10
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S786000, C257S774000, C257S667000, C257S048000, C257S680000, C257S738000, C257S787000, C365S129000, C361S760000, C361S783000, C361S776000, C361S728000
Reexamination Certificate
active
06577015
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor fabrication and, more particularly, to BOC (Board-on-Chip) FBGA (fine-pitch ball grid array) packages.
2. Background of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Microprocessor-controlled circuits are used in a wide variety of applications. Such applications include personal computers, control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in a memory device coupled to the microprocessor. Devices of these types are formed from a plurality of electrical circuits placed together in what is known in the art as a package. The packaging of electrical circuits is a key element in the technological development of any device containing electrical components. Many electrical circuits are packaged for surface mounting, and Fine-Pitch Surface Mount Technology (FPT) and Pin Grid Array (PGA) technology are well developed areas of this type of packaging technology. In addition, an emerging packaging method has been developed using Ball Grid Array (BGA) technology.
In forming surface mount packages, one important step is that of encapsulating the microchip or die and substrate. Proper flow of the encapsulating material is required to obtain maximum uniformity in the characteristics of the molded encapsulating material. Non-uniform material characteristics in the molded encapsulating material can create undesired stresses resulting in cracking of the encapsulating body. Delamination can also result from non-uniformity in the molded encapsulating material. Bridging of electrical pathways can be another resultant of an improperly formed encapsulating molds. Thus, the encapsulating process plays an important role in formation of packaged surface mount devices.
Another key area in surface mount technology is chip size. Smaller microchip devices mean less space used by each component. Significant research and development has been devoted to finding ways to get more and more capabilities into smaller areas. Engineers have been challenged with finding ways to increase hardware capabilities, with memory capacity being one area in which board geography is at a particular premium. However, regardless of whether FPT, PGA, or BGA is implemented, surface mount technologies are limited by the space available on the ceramic substrate or printed circuit board (PCB). As a result, the amount of memory will disadvantageously be limited by the dimensions of the mounting surface. Accordingly, any reduction in surface mount component size may be beneficial.
The present invention may be directed to addressing one or more of the problems set forth above.
SUMMARY OF THE INVENTION
Certain aspects commensurate in scope with the disclosed embodiments are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.
In one embodiment of the present invention, there is provided a system comprising a semiconductor device, a substrate disposed with a slot there through, and an apparatus for encapsulating the semiconductor package. A material is disposed on the substrate to cover one end of the slot.
According to another embodiment of the present invention, there is provided a semiconductor package comprising a semiconductor device and a substrate disposed with a slot there through. A material is disposed on the substrate to cover one end of the slot.
According to still another embodiment of the present invention, there is provided a method of forming a molded semiconductor package. The method comprises: forming a slot in a substrate; covering one end of the substrate; attaching a semiconductor device to the substrate; electrically-coupling the semiconductor device to the substrate and encapsulating the semiconductor package by flowing a molding compound from one surface of the substrate through the slot to the second surface of the substrate.
REFERENCES:
patent: 5173766 (1992-12-01), Long et al.
patent: 5571027 (1996-11-01), Roebuck et al.
patent: 5854740 (1998-12-01), Cha
patent: 6127726 (2000-10-01), Bright et al.
patent: 6224936 (2001-05-01), Gochnour et al.
patent: 6232148 (2001-05-01), Ma et al.
patent: 6246247 (2001-06-01), Eldridge et al.
patent: 6300163 (2001-10-01), Akram
patent: 6300165 (2001-10-01), Castro
patent: 6331939 (2001-12-01), Corisis et al.
patent: 6373127 (2002-04-01), Baudouin et al.
patent: 6388199 (2002-05-01), Jiang et al.
Fletcher Yoder & Van Someren
Micro)n Technology, Inc.
Williams Alexander O.
LandOfFree
Partial slot cover for encapsulation process does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Partial slot cover for encapsulation process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Partial slot cover for encapsulation process will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3109343