Partial reconfiguration of a programmable gate array using a...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07024651

ABSTRACT:
A bus macro for use as a routing resource for partial reconfiguration of a field programmable gate array (FPGA) with a design that has interdesign routing with at least one other design programmed into the FPGA comprises: at least one row of bus lines disposed within the FPGA between at least two design areas; a first set of gates disposed within the FPGA for controlling a routing of signals over the at least one row of bus lines from a first design area to a second design area of the FPGA according to a first routing configuration embedded in the first design area; and a second set of gates disposed within the FPGA for controlling a routing of signals over the at least one row of bus lines from the second design area to the first design area of the FPGA according to a second routing configuration embedded in the second design area. A method of partially reconfiguring a field programmable gate array (FPGA) with at least one design that has interdesign routing with at least one other design programmed into the FPGA is also disclosed utilizing at least one bus macro.

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Xilinx's Application Note: Virtex Series; XAPP151 (v1.5), “Virtex Series Configuration Architecture User Guide” Sep. 27, 2000; pp. 1-45; available from Xilinx, Inc. 2100 Logic Drive, San Jose, California 95124.
Xilinx's Application Note; XAPP153 (v1.0), “Status and Control Semaphore Registers Using Partial Reconfiguration”; Jun. 7, 1999; pp. 1-4; available from Xilinx, Inc. 2100 Logic Drive, San Jose, California 95124.

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