Partial parity correction logic

Details Partial parity correction logic Partial parity correction logic

1997-01-31

1999-08-31

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

714 48, G06F 1300

Patent

active

059448083

ABSTRACT:
A PCI-to-PCI bridge circuit configurable to pass a parity error from one bus to the other bus during a prefetch includes a first interface for interfacing with a first PCI bus, a second interface for interfacing with to a second PCI bus, and a parity correction logic circuit. In response to one of a set of predetermined read commands from a device on the first PCI bus to read data from a device on the second PCI bus, the bridge circuit will initiate a prefetch transaction on the second PCI bus to read the requested data from the device on the second PCI bus. The parity correction logic circuit is coupled to receive from the first interface a first byte enable signal and a second byte enable signal, which are part of the read transaction on the first PCI bus. The parity correction logic circuit is also coupled to receive from the second interface a parity signal corresponding to the prefetch transaction on the second PCI bus. The parity correction logic circuit provides to the first interface a parity signal that causes a data parity error for the read transaction on said first PCI bus when the prefetch read transaction on said second PCI bus has a data parity error.

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