Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-12-30
2010-02-09
Chaudry, M. Mujtaba K (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S780000
Reexamination Certificate
active
07661055
ABSTRACT:
Partial-parallel implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a selected number of cycles is performed during each of bit node processing and check node processing when performing error correction decoding of an LDPC coded signal. The number of cycles of each of bit node processing and check node processing need not be the same. At least one functional block, component, portion of hardware, or calculation can be used during both of the bit node processing and check node processing thereby conserving space with an efficient use of processing resources. At a minimum, a semi-parallel approach can be performed where 2 cycles are performed during each of bit node processing and check node processing. Alternatively, more than 2 cycles can be performed for each of bit node processing and check node processing.
REFERENCES:
patent: 3542756 (1970-11-01), Gallager
patent: 3665396 (1972-05-01), Forney, Jr.
patent: 4295218 (1981-10-01), Tanner
patent: 6430233 (2002-08-01), Dillon et al.
patent: 6473010 (2002-10-01), Vityaev et al.
patent: 6567465 (2003-05-01), Goldstein et al.
patent: 6633856 (2003-10-01), Richardson et al.
patent: 6938196 (2005-08-01), Richardson et al.
patent: 6957375 (2005-10-01), Richardson
patent: 7246304 (2007-07-01), Kim
patent: 7299397 (2007-11-01), Yokokawa et al.
patent: 7401283 (2008-07-01), Shen et al.
patent: 7415079 (2008-08-01), Cameron et al.
patent: 7454685 (2008-11-01), Kim et al.
patent: 2003/0104788 (2003-06-01), Kim
patent: 2005/0149844 (2005-07-01), Tran et al.
patent: 2005/0262420 (2005-11-01), Park et al.
patent: 2006/0107179 (2006-05-01), Shen et al.
patent: 2006/0274772 (2006-12-01), Kim et al.
R. G. Gallager, “Low density parity check codes,” IRE Trans. Info. Theory, vol. IT-8, pp. 21-28, Jan. 1962.
R. Gallager, Low-Density Parity-Check Codes, Cambridge, MA: MIT Press, 1963, 90 pages.
M. Luby, M. Mitzenmacher, M. A. Shokrollahi, D. A. Spielman, and V. Stemann, “Practical Loss-Resilient Codes”, Proc. 29th Symp. on Theory of Computing, 1997, pp. 150-159.
T. J. Richardson and R. L. Urbanke, “The capacity of low-density parity-check code under message-passing decoding,” IEEE Trans. Inform. Theory, vol. 147, No. 2, pp. 599-618, Feb. 2001.
Cameron Kelly Brian
Lee Tak K.
Shen Ba-Zhong
Tran Hau Thien
Broadcom Corporation
Chaudry M. Mujtaba K
Garlick & Harrison & Markison
Short Shayne X.
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