Partial load/store forward prediction

Details Partial load/store forward prediction Partial load/store forward prediction

2011-07-19

2011-07-19

Alrobaye, Idriss N (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Processing control for data transfer

C712S220000

Reexamination Certificate

active

07984274

ABSTRACT:
In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.

REFERENCES:
patent: 4521851 (1985-06-01), Trubisky et al.
patent: 4594660 (1986-06-01), Guenthner et al.
patent: 5276828 (1994-01-01), Dion
patent: 5404470 (1995-04-01), Miyake et al.
patent: 5440752 (1995-08-01), Lentz et al.
patent: 5465336 (1995-11-01), Imai et al.
patent: 5467473 (1995-11-01), Kahle et al.
patent: 5471598 (1995-11-01), Quattromani et al.
patent: 5475823 (1995-12-01), Amerson et al.
patent: 5487156 (1996-01-01), Popescu et al.
patent: 5490259 (1996-02-01), Hiraoka et al.
patent: 5557763 (1996-09-01), Senter et al.
patent: 5606670 (1997-02-01), Abramson et al.
patent: 5619662 (1997-04-01), Steely, Jr. et al.
patent: 5625835 (1997-04-01), Ebicioglu et al.
patent: 5651125 (1997-07-01), Witt et al.
patent: 5652859 (1997-07-01), Mulla et al.
patent: 5710902 (1998-01-01), Sheaffer et al.
patent: 5717883 (1998-02-01), Sager
patent: 5742791 (1998-04-01), Mahalingaiah et al.
patent: 5748978 (1998-05-01), Narayan et al.
patent: 5751983 (1998-05-01), Abramson et al.
patent: 5761712 (1998-06-01), Tran et al.
patent: 5768555 (1998-06-01), Tran et al.
patent: 5781752 (1998-07-01), Moshovos et al.
patent: 5781790 (1998-07-01), Abramson et al.
patent: 5799165 (1998-08-01), Favor et al.
patent: 5802588 (1998-09-01), Ramagopal et al.
patent: 5822559 (1998-10-01), Narayan et al.
patent: 5832297 (1998-11-01), Ramagopal et al.
patent: 5835747 (1998-11-01), Trull
patent: 5850533 (1998-12-01), Panwar et al.
patent: 5884060 (1999-03-01), Vegesna et al.
patent: 5884061 (1999-03-01), Hesson et al.
patent: 5887152 (1999-03-01), Tran
patent: 5923862 (1999-07-01), Nguyen et al.
patent: 5996068 (1999-11-01), Dwyer, III et al.
patent: 6016540 (2000-01-01), Zaidi et al.
patent: 6021485 (2000-02-01), Feiste et al.
patent: 6108770 (2000-08-01), Chrysos et al.
patent: 6122727 (2000-09-01), Witt
patent: 6141747 (2000-10-01), Witt
patent: 6212622 (2001-04-01), Witt
patent: 6212623 (2001-04-01), Witt
patent: 6266744 (2001-07-01), Hughes et al.
patent: 6393536 (2002-05-01), Hughes et al.
patent: 6481251 (2002-11-01), Meier et al.
patent: 6502185 (2002-12-01), Keller et al.
patent: 6523109 (2003-02-01), Meier
patent: 6542984 (2003-04-01), Keller et al.
patent: 6549990 (2003-04-01), Hughes et al.
patent: 6553482 (2003-04-01), Witt
patent: 6622237 (2003-09-01), Keller et al.
patent: 6625723 (2003-09-01), Jourday et al.
patent: 6651161 (2003-11-01), Keller et al.
patent: 6658559 (2003-12-01), Arora et al.
patent: 6678807 (2004-01-01), Boatright et al.
patent: 6694424 (2004-02-01), Keller et al.
patent: 6728867 (2004-04-01), Kling
patent: 6918030 (2005-07-01), Johnson
patent: 7062617 (2006-06-01), Dundas
patent: 7181598 (2007-02-01), Jourdan et al.
patent: 7263600 (2007-08-01), Sander et al.
patent: 7321964 (2008-01-01), Filippo et al.
patent: 0651323 (1995-05-01), None
patent: 0651331 (1995-05-01), None
patent: 0709770 (1996-05-01), None
patent: 0727737 (1996-08-01), None
patent: 2281442 (1995-03-01), None
patent: 96/12227 (1996-04-01), None
patent: 97/27538 (1997-07-01), None
Leibholz, et al., “The Alpha 21264: A 500 MHz Out-of-Order Execution Microprocessor,” Copyright 1997, IEEE, pp. 28-36.
Popescu, et al., “The Metaflow Architecture,” IEEE Micro Jun. 1991, pp. 10-13 and 63-73.
Moshovos, et al., “Speculative Memory Cloaking and Bypassing,” pp. 1-15, Oct. 1999.
Moshovos, et al., “Streamlining Inter-Operation Memory Communication via Data Dependence Predictions,” IEEE pp. 1-11, Dec. 1997.
Gopal, et al., “Speculative Versioning Cache,” pp. 1-11, Feb. 1998.
Chrysos, et al., “Memory Dependence Prediction Using Store Sets,” Copyright 1998, IEEE, pp. 142-153.
Moshovos, et al., “Dynamic Speculation and Synchronization of Data Dependences,” Copyright 1997, ACM pp. 181-193.
Johnson, “Superscalar Microprocessor Design,” Prentice-Hall, 1991, pp. 127-129.
Gwennap, “Digital 21264 Sets New Standard,” Microdesign Resources, vol. 10, No. 14, Oct. 1996, pp. 103-108.

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