Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-12-06
2005-12-06
Padmanabhan, Mano (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C711S130000, C711S144000, C709S213000, C709S214000
Reexamination Certificate
active
06973543
ABSTRACT:
A partial directory cache records addresses of blocks which are known to be cached in a non-exclusive state in any caches currently caching the blocks. If a read command to a block recorded in the partial directory cache is received, one or more probes corresponding to the command may be inhibited. Since probes are selectively inhibited if an affected block is recorded in the partial directory cache, the size of the partial directory cache may be flexible. If a particular block is not represented in the partial directory cache, probes are performed when the particular block is accessed (even if the particular block could have been represented in the partial directory cache). Thus, coherency is maintained even if every non-exclusively cached block is not represented in the partial directory cache.
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Heter Erik A.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Namazi Mehdi
Padmanabhan Mano
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