Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-12-13
2010-11-23
Chaudry, M. Mujtaba K (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S776000, C714S774000
Reexamination Certificate
active
07840873
ABSTRACT:
In an embodiment, a node comprises a packet scheduler configured to schedule a packet to be transmitted on the link, the packet comprising a command and associated packet data. Coupled to the packet scheduler and configured to transmit the packet on the link, and interface circuit is configured to generate error detection data covering the packet. The interface circuit is configured to transmit the error detection data covering the packet at an end of the packet, and is further configured to insert at least one partial error detection data within the packet. The partial error detection data covers a portion of the packet that precedes the partial error detection data. A receiver is configured to receive the data and forward the data based on partial CRC check.
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Donley Greggory D.
Fertig Michael K.
Hughes William A.
Yang Chen-Ping
Chaudry M. Mujtaba K
GLOBALFOUNDRIES Inc.
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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