Parity prediction for binary adders with selection

Details Parity prediction for binary adders with selection Parity prediction for binary adders with selection

1988-04-25

1990-05-08

Smith, Jerry

Boots, shoes, and leggings

371 494, G06F 1110

Patent

active

049244248

ABSTRACT:
An apparatus for predicting parity of a result produced by selection of the most or least significant thirty-two bits produced by a thirty-four bit adder, the parity being predicted concurrently with and independently of the result. Parity for byte Si of the selected result is derived by circuitry implementing the relationship:

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patent: 3911261 (1975-10-01), Taylor
patent: 3925647 (1975-12-01), Louie
patent: 4079457 (1978-03-01), Miller
patent: 4224680 (1980-09-01), Miura
IBM Technical Disclosure Bulletin, vol. 30, No. 3, Aug. 1987, Minimized Parity Predict Circuit for Incrementation.
IBM Technical Disclosure Bulletin, vol. 23, No. 12, May 1981, Parity Predict of a Sum, R. Kalandra and A. Weinberger.
IBM Technical Disclosure Bulletin, vol. 22, No. 4, Sep. 1979, Parity Prediction for Fast Three-Input Adder, K. E. Olin and A. Weinberger.
IBM Technical Report, TR 01.1200, Aug. 26, 1969, Concurrent Error Detection for Group Look-Ahead Binary Adders, G. G. Langdon, Jr., and C. K. Tang.

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