Parity prediction circuit and logic operation circuit using...

Details Parity prediction circuit and logic operation circuit using... Parity prediction circuit and logic operation circuit using...

2011-06-14

2011-06-14

Baderman, Scott T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07962829

ABSTRACT:
In a parity prediction circuit which corrects the predicted parity using AND/OR parity inversion condition generation circuits, predicted parity and inversion conditions are corrected using an EOR condition of one of data buses. Two parity prediction logics are sufficient; the added correction logic circuit requires only the EOR condition for one data bus, and the hardware configuration can be reduced. Further, control signals from opcode signals are employed in the latter half of the logic operations, and thereby parity prediction is possible at high speed comparable with circuits which have parity prediction logic for each instruction.

REFERENCES:
patent: 5440604 (1995-08-01), De Subijana et al.
patent: 2008/0282136 (2008-11-01), Yamashita
patent: 58-29054 (1983-02-01), None
patent: 2004-234110 (2004-08-01), None
English language version of International Search Report (PCT/ISA/210) of International Application PCT/JP2005/006297 (mailed on Jul. 5, 2005).

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