Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1997-06-05
1999-11-30
Thai, Tuan V.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711112, 714 6, 714 7, 714 9, 714 10, 371 404, 371 492, 371 511, G06F 1100, G06F 1200
Patent
active
059960469
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a control system for an array type disk system having a plurality of disk devices used as storage systems of a computer system arranged in array, and more particularly to a computer system intended to reduce a CPU load.
BACKGROUND ART
A disk array system is an external storage apparatus having a plurality of disk devices arranged in array to process a read request (data read request) and a write request (data write request) by a parallel operation of the disks at a high speed and enhance reliability by adding parity (redundant data). The disk array system is called a RAID (Redundant Arrays of Inexpensive Disks) and it is classified into five levels depending on type and structure of the parity data. (Article: "A case for Redundant Arrays of Inexpensive Disks (RAID)", David A. Patterson, Garth Gibson and Randy H. Katz, Computer Science Division Department of Electrical Engineering and Computer Sciences, University of California Berkeley).
In the level 5 (hereinafter referred to as a RAID5) of the above classification methodology, parities are scattered to respective disks and stored therein so that the concentration of the process to one parity disk during the parity updating is prevented and the performance reduction during the write process is suppressed. Accordingly, the performance is enhanced for the random access in which the reading/writing of small size data occurs frequently. ("Special Issue on Disk Array System", Nikkei Electronics Apr. 26, 1993, No. 579, pages 77.about.91).
In the disk array system, in order to operate the disks in parallel and add the parity data, a special address translation is required and such address translation has been conducted by dedicated hardware in the prior art. A known example of such system is disclosed in JP-A-2-236714. However, as the performance of a CPU (Central Processing Unit) of a host system is enhanced, a disk array system which conducts the address translation inherent to the disk array by software program. In the present specification, such disk array system is referred to as a software RAID. A known example of the disk array system which conduct the address translation for the parallel operation of the disks is disclosed in JP-A-5-250099.
As prior art, the software RAID of the RAID5 is explained with reference to a system configuration of FIG. 21. In FIG. 21, numeral 1 denotes a host system, numeral 4 denotes disk interface control means and numeral 3 denotes a disk device group.
The host system 1 comprises a host CPU 101, a cache 102 which can be read and written at a high speed, a local bus-system bus bridge 103, a main memory 104 for storing data and programs, and a bus interface 107. A local bus 105 connects the host CPU 101, the cache 102 and the local bus-system bus bridge 103. A system bus 106 connects the local bus-system bus bridge 103 and the bus interface 107. A disk array control program area 109 is arranged in the main memory 104 and stores a disk array control program necessary to control the disk array system.
The disk interface control means 4 is connected with the bus interface 107 of the host system 1.
The disk device group 3 comprise five disk devices 301.about.305 in the present prior art example. The disks 301.about.305 are connected to the disk interface control means 4 by daisy chain connection.
In the disk array system, a plurality of disks are striped, and parity data is added to each striping to enhance the reliability. During the disk array write process, a parity is generated by an exclusive OR operation of data of each stripe of each disk device. The host CPU 101 conducts the address translation and the parity generation for the striping by using the disk control program stored in the disk array control program area 109.
The read process and the write process conducted by the overall system including the disk parallel operation and the parity data addition are referred to as a disk array read process and a disk array write process, respectively. In the disk array read pro
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Arakawa Hiroshi
Kaneda Yasunori
Matsunami Naoto
Oeda Takashi
Takano Masahiro
Hitachi , Ltd.
Thai Tuan V.
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