Parity detection system for wide bus circuitry

Details Parity detection system for wide bus circuitry Parity detection system for wide bus circuitry

1986-04-04

1987-12-01

Smith, Jerry

Excavating

371 68, G06F 1110

Patent

active

047109351

ABSTRACT:
A parity checking system for establishing integrity of data transfer on a wide bus. Each set of "4" bus lines of a multiple line bus is passed from a driver chip to a corresponding receiver chip. An added parity driver chip senses each corresponding bit line of each driver chip to develop a set of four parity signals for comparison with corresponding parity signals from each corresponding bit line of each one of a set of receiver chips. Any discrepancy will generate a parity error signal.

REFERENCES:
patent: 3882460 (1975-05-01), Bennett
patent: 4245344 (1981-01-01), Richter
patent: 4360917 (1982-11-01), Sindelar
F. F. Sellers, "Error Detecting Logic for Digital Computers", 1968, pp. 208 and 210.
C. H. Schuenemann, "Correction of Single Errors by Double Parity Check", IBM TDB, vol. 13, No. 5, 10/1970, pp. 1324-1325.

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