Parity checking circuit

Details Parity checking circuit Parity checking circuit

1999-01-26

2002-04-23

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S726000

Reexamination Certificate

active

06378108

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 98-01102, filed Jan. 27, 1998, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital systems, and more specifically to circuits for checking the parity of the contents of a register.
2. Description of Related Art
In a typical conventional digital system, data that is exchanged is provided with a parity bit. The parity bits are generated by a data transmitting circuit such that the number of “1” level bits of each datum, including the parity bit, is even. A data receiving circuit checks the number of “1” bits in each received datum to determine if the datum was corrupted during transmission. Typically, such parity checking is performed at the level of the registers that temporarily store the received data.
FIG. 1
shows a conventional structure for a register and an associated parity checking circuit. The register includes flip-flops
10
that each receive one bit D
0
to Dn of a datum (including the parity bit) at the D input. All of the flip-flops
10
receive a common clock signal CK, and the Q outputs Q
0
to Qn of the flip-flops
10
are supplied to another circuit (not shown) that utilizes or transmits the datum stored in the register. Additionally, a parity checking circuit
12
, which is typically an exclusive-or (XOR) gate with the necessary number of inputs, receives all of the Q outputs of the flip-flops
10
. The parity checking circuit generates an error signal ERR whenever the parity is incorrect (i.e., when there is not an even number of “1” bits in the registers).
Although the conventional structure of
FIG. 1
allows parity checking to be performed by the data receiving circuit, the interconnections between the flip-flops and the parity checking circuit occupy a significant metallization surface area. Further, such interconnections significantly increase the capacitances at the outputs of the flip-flops.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to remove the above-mentioned drawbacks and to provide a parity checking circuit that allows the metallization surface area occupied by the interconnections between the parity checking circuit and an associated register to be reduced. The associated register has a test mode in which the flip-flops of the register are serially-connected to form a scan path (i.e., a scan input of each flip-flop is connected to a scan output of the preceding flip-flop). The parity checking circuit includes an XOR gate for at least each flip-flop from the second flip-flop to the last flip-flop of the register. Each XOR gate has one input coupled to the normal output of the associated flip-flop, another input coupled to the scan input of the flip-flop, and an output coupled to the scan output of the flip-flop whenever the register is not in the test mode. The result of the parity checking operation is generated at the output of the XOR gate associated with the last flip-flop of the register. In preferred embodiments, for each flip-flop of the register, the normal output of the flip-flop is supplied to the scan output in the test mode, and the output of the associated XOR gate is supplied to the scan output when not in the test mode.
One embodiment of the present invention provides a register that is formed by a first cell and other cells. Each of the other cells in the register include a scan input, a scan output, a flip-flop, and an XOR gate. The scan input is coupled to the input of the flip-flop and the output of the flip-flop is coupled to the scan output when the register is in a test mode. Further, the output of the flip-flop is coupled to a first input of the XOR gate and the scan input is coupled to a second input of the XOR gate. The output of the XOR gate is coupled to the scan output when the register is not in the test mode. In a preferred embodiment, the XOR gates of the other cells perform a parity checking operation on the register and a result of the parity checking operation is provided at the scan output of the other cell at the end of the scan path.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.


REFERENCES:
patent: 4926424 (1990-05-01), Maeno
patent: 5267249 (1993-11-01), Dong
patent: 5574733 (1996-11-01), Kim
patent: 6199182 (2001-03-01), Whetsel
European Patent Abstract of Japanese Publication No. 03099522, published Apr. 24, 1991.
French Search Report dated Sep. 30, 1998 with annex on French Application No. 98-01102.
“Parity Generator Integrated With Latches”, IBM Technical Disclosure Bulletin, vol. 29, No. 8, Jan. 8, 1987, pp. 3342-3344, Armonk, New York, USA.

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