Parity bit system for a CAM

Details Parity bit system for a CAM Parity bit system for a CAM

2006-01-31

2006-01-31

Chace, Christian P. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C714S052000, C714S054000, C714S701000, C714S758000, C714S800000, C714S763000

Reexamination Certificate

active

06993623

ABSTRACT:
A CAM includes a parity bit system for error detection. In one embodiment, in each CAM cell, the data portion has its own data parity bit while the status portion has an independent status parity bit. The status parity bit is recalculated and updated whenever a status bit in the entry is changed. In another embodiment, each status bit is provided with a corresponding shadow status bit. Each status bit and its corresponding shadow status bit is always loaded with the same data. In this manner, every change 1-bit change to a status bit is made as two identical 1-bit changes to the status bit and its corresponding shadow status bit. The two identical 1-bit changes are parity neutral, thereby permitting status changes without requiring recomputing and saving a new parity.

REFERENCES:
patent: 5455834 (1995-10-01), Chang et al.
patent: 6067656 (2000-05-01), Rusu et al.
patent: 2002/0126704 (2002-09-01), Cam et al.
patent: 2004/0083421 (2004-04-01), Foss et al.

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