Parity and error correction coding on integrated circuit address

Details Parity and error correction coding on integrated circuit address Parity and error correction coding on integrated circuit address

1990-03-29

1992-12-22

Beausoliel, Robert W.

Excavating

371 511, H03M 1300

Patent

active

051739054

ABSTRACT:
A more secure method for selecting and addressing individual integrated circuit chips and memory locations, registers or input/output ports within the chips includes supplying the chips with address information including address checking information, checking the address information actually received in the chip by using an address checking circuit in the integrated circuit, and inhibiting use of the address information in the chip when the address checking circuit indicates an erroneous address. By inhibiting the use of erroneous address information, state information stored in the integrated circuit is not lost. The integrated circuit sends a fault signal requesting retransmission of the address information for recovery from the address fault. Preferably the address checking information is an error detecting and correcting code for correcting single-bit errors and detecting double-bit errors. Then the integrated circuit functions properly with one defective address input.

REFERENCES:
patent: 3270318 (1966-08-01), Strawbridge
patent: 3914741 (1975-11-01), Bonser et al.
patent: 4163147 (1979-07-01), Scheuneman et al.
patent: 4335459 (1982-06-01), Miller
patent: 4486883 (1984-12-01), Kamai et al.
patent: 4493081 (1985-01-01), Schmidt
patent: 4506362 (1985-03-01), Morley
patent: 4528666 (1985-07-01), Cline et al.
patent: 4528667 (1985-07-01), Fruhauf
patent: 4608687 (1986-08-01), Dutton
patent: 4635232 (1987-01-01), Iwahashi et al.
patent: 4639895 (1987-01-01), Iwahashi et al.
patent: 4646304 (1987-02-01), Fossati et al.
patent: 4689792 (1987-08-01), Traynor
patent: 4706249 (1987-10-01), Nakagawa et al.
patent: 4720829 (1988-01-01), Fukasawa et al.
patent: 4726021 (1988-02-01), Horiguchi et al.
patent: 4730320 (1988-03-01), Hidaka et al.
patent: 4875212 (1989-10-01), Hashimoto
patent: 4926426 (1990-05-01), Scheuneman et al.
patent: 4955023 (1990-09-01), Tanimoto
Kalter et al., "A 50 ms 16 Mb DRAM with a 10 ms Data Rate," 1990 IEEE International Solid-State Conference, Feb. 16, 1990, pp. 232-233, 303.
Bruckert et al., "Designing Reliability into the VAX 8600 System," Digital Technical Journal, No. 1, Aug. 1985, pp. 71-77.

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