Paritioned bit line structure of EEPROM and method of reading da

Details Paritioned bit line structure of EEPROM and method of reading da Paritioned bit line structure of EEPROM and method of reading da

1991-04-02

1993-10-12

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Differential sensing

365203, G11C 1140

Patent

active

052532100

ABSTRACT:
A memory cell array is electrically separated into an upper memory cell array 1a and a lower memory cell array 1b by a connection transistor group 2, when an external address signal changes. Therefore, each bit line pair in the memory cell array is separated into corresponding two bit line pairs. The potential of the bit line belonging to the selected memory cell is set to the read potential. Meanwhile, the potential of the bit line forming the pair of the bit line separated from the bit line is set to an intermediate potential between "0" read potential and "1" read potential. Then, the upper memory cell array 1a and the lower memory cell array 1b are electrically connected, whereby the bit line pairs corresponding to each memory cell array are integrated into one bit line pair. The potential difference of the two bit lines forming the integrated bit line pair is amplified by a corresponding differential amplifying type sense amplifier. As a result, the information read out from the selected memory cell is sensed.

REFERENCES:
patent: 4112508 (1978-09-01), Itoh
Masanobu Yoshida et al., "An 80ns Address-Date Multiplex 1Mb CMOS EPROM", 1987 IEEE International Solid-State Circuits Conference, Feb. 25, 1987, pp. 70-71.
Kenichi Imamiya et al., "A 68ns 4Mbit CMOS EPROM with high noise immunity design", 1989 Symposium on VLSI Circuits, May, 1989, pp. 37-38.
Kazuo Kobayashi et al., "A Self-Timed Dynamic Sensing Scheme for 5V Only Multi-Mb Flash E.sup.2 PROMs", 1989 Symposium on VLSI Circuits, May, 1989, pp. 39-40.

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