Parasitic current barriers

Details Parasitic current barriers Parasitic current barriers

1998-08-26

2001-08-21

Lee, Eddie C. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S754000, C257S756000, C257S773000, C257S776000

Reexamination Certificate

active

06278186

ABSTRACT:

BACKGROUND
This is an improvement of the invention shown in U.S. Pat. No. 5,717,243, the entire disclosure of which is herein incorporated by reference. Integrated circuits have one or more levels of metal formed on dielectric material that covers a semiconductor substrate. The levels of metal are separated by dielectric material. The substrate that holds the integrated circuits is made of semiconductor material. The metal levels are patterned into lines that can be characterized as either signal lines (which carry a signal), return lines (which are signal lines carrying current in the opposite direction to another signal line), or lines attached to ground (ground lines). Parasitic currents can flow in the substrate due either to capacitive coupling or to inductive coupling to these metal lines.
Consider FIGS.
1
(
a
) and
1
(
b
) where one or more first metal line(s)
104
carries a signal and one or more ground lines
108
that run parallel to signal line(s)
104
. The lines
104
,
108
are supported on dielectric layer
16
that covers the semiconductor substrate
14
. The substrate
14
is doped at around 10 to 20 ohm-cm. With this resistivity, the primary power loss is due to resistive current flow through the substrate that is capacitively generated from the signal line. The resistive current flow in the substrate caused by the signal line can be redirected by the presence of a nearby ground line which then tends to become the primary destination of this current. Without doing anything special, this will reduce the resistance somewhat but will not greatly reduce the resistive losses. This particular loss factor can be nearly eliminated by pursuing one of two strategies: The first strategy is to make the path so highly resistive that current cannot flow at all. The second strategy, pursued here, is to make the path so conductive that the resistive loss is very small even though the current is free to flow. The problem introduced by making the path conductive is that another parasitic current is formed. In many instances, this other parasitic current is worse than the eliminated parasitic current. This other parasitic current is an inductively induced image current L of the signal line in the conductive part of the substrate. This image current L is opposite to the current in the signal line and parallel in direction. The path of the capacitively generated current in the substrate from the signal line to the ground line is perpendicular to the signal line as shown by arrow C; the inductively induced current in the substrate is parallel to the signal line as shown by arrow L.
The substrate resistive loss due to inductive coupling to a heavily doped layer can be calculated. In this calculation, the substrate is doped with a buried layer with a resistance of 8.1 Ohms/square. The signal line
104
is above the dopant
20
(
a
), as shown in FIG.
2
(
a
), and is 2.5 um thick, 20 um wide, and 1,000 um long. The power loss in the substrate, P
s
, is
P
s
=V
s
2
/R
s
  Equation (1)
where R
s
is the resistance in the conductive path through the substrate and V
s
is the voltage difference in the substrate below the metal line caused by mutual inductive coupling from the signal line above.
V
s
is related to the current in the metal line (I
m
) by the formula
V
s
=M&ohgr;I
m
  Equation (2)
where M is the mutual inductance between the signal line
104
and the conductive path in the substrate
14
, and &ohgr; is the frequency in radians/second. Substituting this into the formula for P
s
gives
P
s
=(
M&ohgr;I
m
)
2
/R
s
  Equation (3)
The active doped region of the substrate is assumed to be 30 &mgr;ms wide and 1000 &mgr;ms long. From analytic inductance equations, M=8.2 e -10 Henrys. R
s
, the resistance in the substrate below the signal line, is calculated from the sheet resistance and the geometry as
R
s=
(8.1 Ohms)(1000 &mgr;m)/(30 &mgr;m)=270 Ohms  Equation (4)
Choosing a frequency of 5 GHz and substituting these values into Equation (3), we get
P
s
=2.50
I
m
2
  Equation (5)
where mks units are assumed. For comparison, the resistive loss in the metal is
P
m
=R
m
I
m
2=
0.75
I
m
2
  Equation (6)
The above analysis shows that in the prior art structure the resistive loss through the substrate is roughly comparable to but greater than the loss in the signal line
104
(in this case, more that 3 times greater). It would be desirable to reduce such losses.
SUMMARY OF THE INVENTION
A solution to the problem of parasitic current is as follows: let the perpendicular current in the substrate flow easily and prevent the parallel flow. This result is accomplished by directionally patterning the substrate doping to achieve this result. In particular, the substrate is patterned to have sequential strips of alternating relative high and low conductivity disposed beneath the signal and ground lines such that the boundaries between adjacent strips are in the direction transverse to the signal and ground lines. The highly conductive regions allow the capacitively generated current to flow in the transverse direction. The low conductive regions interrupt the parallel flow of inductively induced current. Such a structure allows easy flow of capacitively generated current to ground and thereby improves substrate loss and a shielding effect that reduces coupling to other devices through the substrate—without allowing the parasitic image current to flow in the substrate parallel to the metal lines.
Alternatively, other conductive layers can be patterned to replace the dopant. Instead of being in the semiconductor, the conductive layers are on or above the semiconductor layer. Each conductive layer is more conductive than the semiconductor substrate.
Additionally, multiple patterned conductive layers can be used to provide a more complete shield from the capacitively generated current. One embodiment provides for isolating one current carrying line from capacitively inducing current in one or more other current carrying lines.


REFERENCES:
patent: 4543595 (1985-09-01), Vora
patent: 4754546 (1988-07-01), Lee et al.
patent: 4894114 (1990-01-01), Nathanson
patent: 4954873 (1990-09-01), Lee et al.
patent: 5194402 (1993-03-01), Ehrfeld et al.
patent: 5420558 (1995-05-01), Ito et al.
patent: 5431987 (1995-07-01), Ikeda
patent: 5446311 (1995-08-01), Ewen et al.
patent: 5519582 (1996-05-01), Matsuzaki
patent: 5675298 (1997-10-01), Bhagwan et al.
patent: 5717243 (1998-02-01), Lowther
patent: 5773891 (1998-06-01), Delgado et al.
patent: 5909059 (1999-06-01), Hada et al.
patent: 0 837 503 A2 (1998-04-01), None
patent: WO 97/45873 (1997-12-01), None
Electronic Engineering Times, Sep. 15, 1997 “Contact change boots inductor quality”, Chappell Brown, p. 41.
IEEE Journal of Solid-State Circuits, “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's”, vol. 33, No. 5, May 1998, C. Patrick Yue, Student Member, IEEE, and S. Simon Wong, Senior Member, IEEE.
International Search Report EP 99402081 Apr. 2000.

Affiliated with

Also associated with

Rating

Parasitic current barriers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Parasitic current barriers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parasitic current barriers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2549501