Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
1998-11-06
2001-05-08
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S041000
Reexamination Certificate
active
06229336
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to integrated circuits, and in particular, to a programmable integrated circuit device with slew control and skew control.
BACKGROUND OF THE INVENTION
Many integrated circuit (IC) devices can be programmed. Examples of such programmable IC devices include some volatile and non-volatile memory devices, field programmable gate arrays (“FPGAs”), programmable logic devices (“PLDs”), and complex programmable logic devices (“CPLDs”).
A programmable IC device typically includes a plurality of input/output (I/O) cells which are coupled to respective I/O pins for the receipt of input signals and the transmission of output signals. In operation, various output signals may be provided at the same or different times to several respective I/O cells. Numerous problems, however, are associated with such provision of output signals at the I/O cells.
For example, under certain circumstances, when several output signals are simultaneously provided to several respective I/O cells, there can be a degradation in the quality of these signals. Specifically, output bus lines external to a programmable logic device may be connected to the I/O cells. These output bus lines may be powered by a single power supply with a limited peak current capacity. As such, the simultaneous fast switching of several output signals may exceed the peak current capacity of the power supply, thus resulting in slow switching on all bus lines. Furthermore, the simultaneous switching of several output signals may create noise and interference in the output signals due to ground bounce and other phenomena.
Under other circumstances, it is desirable to have several output signals appear simultaneously at respective I/O cells. For example, a plurality of output signals may each convey one bit of the same multi-bit address, and thus, ideally, should be presented at the same time on respective I/O pins. In actual operation, however, such output signals are provided at different times due to internal delays within the programmable IC device.
A complex programmable IC device can be connected together with other devices on a printed circuit board. An inherent characteristic of circuit connects on such a board is that the amount of noise introduced into a signal is directly proportional to the length of a connection. Thus, longer connections can produce a degradation of quality in the transmission of signal transitions when slew rates are too fast. Accordingly, a reduction in slew rate would improve transition over long distances.
Another inherent characteristic of printed circuit board interconnects is that transmission delay of a signal is directly proportional to the trace length of a connection over which the signal travels. The trace lengths of various connections within the same bus can be different. Thus, even though the transition of signals conveyed over the same bus ideally should be concurrent, this is often not the case in actual application. Accordingly, delaying the output sources of various signals on a bus could result in a lessskewed transition of the signals at the respective destinations.
SUMMARY OF THE INVENTION
Thus, a need has arisen for a programmable IC device that addresses the disadvantages and deficiencies of the prior art. In particular, the need has arisen for a programmable IC with the capability to control the timing of output signals at respective I/O cells.
In accordance with one embodiment of the present invention, a programmable integrated circuit device includes a plurality of output terminals, each output terminal for use in transmitting a respective output signal. Timing control circuitry is connected to the output terminals. The timing control circuitry is operable to delay the output signal transition on each output terminal and is further operable to control an output signal transition slew rate on each output terminal. The timing control circuitry may comprise one or more programmable delay elements and one or more programmable drivers. Each programmable delay element can delay an output signal transition on a respective output terminal. Each programmable driver can control the slew rate of an output signal transition on a respective output terminal.
In accordance with another embodiment of the present invention, a method for controlling the timing of output signals in a programmable integrated circuit device includes the following steps: generating a plurality of output signals for transmission at a plurality of respective output terminals; controlling the skew of at least a first portion of the output signals en route to the respective output terminals; and controlling the slew rate of at least a second portion of the output signals at the respective output terminals.
In accordance with yet another embodiment of the present invention, a programmable logic device includes a plurality of input/output (I/O) cells. A number of logic circuits are each operable to generate a separate output signal on a respective output line, each output line being coupled to at least one of the I/O cells. Timing control circuitry, coupled to the output line of at least one of the logic circuits, can programmably delay the output signal of such logic circuit. The timing control circuitry can also programmably control the slew rate of the same output signal.
A technical advantage of the present invention includes providing a separate programmable delay element for at least a portion of the output terminals of a programmable IC device. Each programmable delay element can delay an output signal on the respective output terminal, thereby providing skew control of the output signal. Another technical advantage includes providing a separate programmable driver for at least the same, or a separate, portion of the output terminals. Each programmable driver can be used to speed up or slow down the transition from HIGH to LOW (or vice versa) of an output signal on the respective output terminal, thereby providing slew control of that output signal. With the combined skew control and slew control, the timing of output signals at respective output terminals in the programmable logic device can be controlled as desired. For example, one or more output signals can be delayed, or their transition time increased or decreased, so that there is no simultaneous fast switching of a large number of output signals. Accordingly, noise and interference is reduced within the programmable IC device.
Furthermore, multiple output signals can be controlled to appear simultaneously at the output terminals, thereby providing synchronization of the signals when appropriate. In addition, for a printed circuit interconnect bus, it is possible to selectively skew signals at their respective output sources to reduce the skew between signals at their respective destinations.
Other aspects and advantages of the present invention will become apparent from the following descriptions and accompanying drawings.
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Camarota Rafael C.
Chan Albert
Felton Bradley
Shen Ju
Tsui Cyrus Y.
Cho James H.
Lattice Semiconductor Corporation
Skjerven Morrill & MacPherson
Tokar Michael
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