Parametric timing analysis

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Reexamination Certificate

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07346874

ABSTRACT:
Electronic Design Automation tools are used to aid in the design and verification of integrated circuits. As part of the verification process, circuit designs are analyzed with respect to their timing performance. Timing analysis is susceptible to variation in circuit components due to fabrication process variation. Process variation is introduced as worst-case conditions or statistical probabilities. More accurate process variation is modeled by for timing sensitivity with Parametric Elmore Delay. Parametric Elmore Delay introduces effects on circuit components as parameters in the conventional Elmore Delay definition to model fabrication process variation in the timing analysis. Delay variance demonstrates sensitivities to process and design factors. Parametric timing analysis is used to anticipate fabrication yield and identify potential improvements in the design or fabrication process.

REFERENCES:
patent: 2003/0188280 (2003-10-01), Lu
patent: 2004/0216062 (2004-10-01), Fan
patent: 2005/0086615 (2005-04-01), Anand et al.
Nowak, Brian; “Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model”; 2002; IEEE; All Pages.
Gupta, Rohini; “The Elmore Delay as a Bound for RC Trees with Generalized Input Signal”; 1997; IEEE, pp. 95-104.

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