Parameterless language in a machine for implementation thereof

Details Parameterless language in a machine for implementation thereof Parameterless language in a machine for implementation thereof

1999-08-30

2001-05-08

Donaghue, Larry D. (Department: 2154)

Electrical computers and digital processing systems: processing

Processing control

Processing sequence control

C712S247000, C712S002000

Reexamination Certificate

active

06230264

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of programmable computers. In particular, this invention relates to a reduced instruction set computing machine and language in which there is no need for classical linear addressing and no need for operand decoding.
PROBLEM
Most of today's commercial computing devices and programming languages are built upon the foundation of the von Neumann Machine. The von Neumann Machine, named after mathematician John von Neumann, defines a class or an architecture for electrical computing devices. The von Neumann Machine solves algorithmically defined problems by repeatedly performing a cycle of operations. Each computer built according to this architecture has an instruction set which defines the available operational codes (“opcodes”) for a given programming language and system.
The von Neumann Machine is generally characterized by a Central Processing Unit (“CPU”) containing an Arithmetic Logic Unit (“ALU”), and a memory. In general terms, the machine operates by repeating a cycle of events. First, an instruction is fetched from memory. Each instruction includes both an opcode and an operand. The opcode is an instruction to the CPU directing a certain operation be performed. The operand is the data on which the ALU operates. The operand may be the data itself or it may provide an address from which the data can be retrieved. After fetching an instruction, the CPU fetches the necessary data from memory. Then the CPU, specifically the ALU, executes the opcode on the data. The results of the operation are stored in memory and operation of the machine then returns to the first step to fetch the next instruction. This has been the model underlying electronic computers for more than 50 years.
Modern computers developed up until the mid-1980's are commonly called Complex Instruction Set Computing (“CISC”) machines. CISC machines have relatively large instruction sets including complex, multi-cycle instructions. A large, complex instruction set allows for the development of relatively compact code as each single instruction can actually represent multiple operations by the CPU. The compactness of the code or program was particularly important during this period because of the high cost memory. The downside to the compact code of CISC machines, however, is that significant processing time is consumed by the decoding of these complex instructions. The term “decoding” refers to the process carried out by the CPU of reading or parsing each instruction and converting each instruction into language that can be utilized at the hardware level of the machine to perform the requested operations. It is the “microcode” of a CISC machine that effectively translates between a human-readable instruction and an instruction executable by the electronic hardware. Also part of the decoding process is operand decoding which involves the identification, location and retrieval of the data to be operated on by the instruction. Complex decoding takes processing time and limits the performance available with CISC machines.
Beginning in the mid-1980's, corporate and university researchers began developing Reduced Instruction Set Computing (“RISC”) machines and methodologies. Researchers found that the vast majority of the operations performed by a CPU could be covered by a relatively small set of instructions. RISC computers were developed to optimize the operation of that small instruction set by hard-wiring those frequently used operations in the hardware. More complex operations were, unlike with CISC computers, simulated in software instead of being wired into the CPU itself. The code resulting from the use of a smaller instruction set is less compact than that of a CISC machine but is processed much more quickly than the equivalent code in a CISC machine. Less compact code is less of a problem for the design of modern computers as the cost of memory has been reduced dramatically and continues to fall.
The basic operation of a RISC computer is the same as a CISC computer. An instruction is fetched from memory and decoded. Each instruction includes an opcode and an operand. The instructions in a RISC computer are typically of a fixed length. Each instruction is typically one word long whereas in a CISC computer the instruction length might be one word or it might be two, three or more words. Other RISC characteristics including more structured and efficient memory access, pipe-lined execution and the lack of microcode contribute to an increased processing speed for RISC machines as compared to CISC machines.
Even the most powerful RISC computers, however, are limited by the requirements of linear addressing and operand decoding. A program of an existing computer operates through the successive execution of each line or step in the program. At the completion of each step, the program execution continues to the next step. The current location in the program is determined by a program counter that, in effect, successively counts through the memory locations in which the program is stored. A decision step in the program can cause the program counter to jump to a different location or address in the program memory. Once the step at the new location is executed, the program counter again continues its successive incrementing through the steps of the program. Just as each program step is stored at an addressed memory location, so is each piece of data individually addressed. The CPU of current computers only executes operations on data that is in memory or registers accessible to the CPU. The data must be retrieved from memory and stored in a register so that the CPU can utilize the data in the execution of an instruction. Every time a CISC or RISC machine decodes an instruction's operand, the operand must be translated to a memory location, the memory location must be located, and the data residing at that memory location must be copied to a register. The CPU is then able to execute the opcode on the data copied in a register. Each of the above steps consumes processing cycles or “CPU time”.
There exists a need for a computer with no need for addressing in the linear sense described with respect to existing computers. There exists a further need for a computer with no need for operand decoding. There is a further need for a computer that does not require the loading of data from memory to CPU registers or the storing of data from CPU registers to memory.
SOLUTION
The above identified problems, and others, are solved and a technical advance achieved in the field, by the parameterless language and machine for implementation thereof of the present invention. The present invention provides a programming language and apparatus for optimally implementing the language which utilizes a multiply dimensioned code space and a multiply dimensioned data space to create a “parameterless computer”. The parameterless computer of the present invention has no need for addressing and no need for operand decoding as all operands are implicit. There is no data loading from memory or data storing to memory as the data is operated on in the data space where it resides. The state of the computer is defined not only by the data and the code but also by the direction of a code pointer and a data pointer. The result is a computing environment where instruction execution speed approaches or equals clock speed.
A parameterless computer of the present invention includes a code space and a data space. A code space contains the instructions for operating the parameterless computer of the present invention. The data space contains the data of a parameterless computer of the present invention. The code space may be separate from the data space or may be common with the data space. A code pointer is defined by both a position and a direction within the code space. The code pointer navigates through the code space according to the instructions encountered by the code pointer in the code space. A data pointer is defined by both a position and a direction within the data space. T

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