Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-08
2003-04-08
Nelms, David (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06546542
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a designing method and an apparatus of a data driven information processor. Particularly, the present invention relates to a method and an apparatus of efficiently designing a data driven information processor of custom LSI (Large-Scale Integrated circuit) that is optimized for various applications.
2. Description of the Background Art
A von Neumann information processor is well known. The von Neumann information processor has a program of a series of instructions prestored in a program memory. By sequentially addressing the program memory through a program counter, the addressed instruction is read and executed.
An information processor of architecture differing from that of the von Neumann information processor is generally called a “non-von Neumann” information processor. The non-von Neumann information processor includes a data driven information processor (Data Driven Media Processor: DDMP).
The DDMP employs architecture based on parallel processing of instructions. The DDMP is not associated with the concept of a program counter. As soon as the data that are the subject of operation are available in the form of a packet in the DDMP, the instruction of relevant data processing can be executed. Since a plurality of instructions are driven at the same time in accordance with the flow of data, programs are executed in parallel according to the natural data flow in the DDMP. Accordingly, the time required for operation can be reduced significantly compared to that of the von Neumann information processor.
The DDMP transfers a packet by a self-timed pipeline control scheme. The self-timed pipeline scheme differs from the clocked pipeline control scheme.
For clocked pipeline control, cascaded latch circuits are prepared. These latch circuits are driven by a clock signal to shift a data packet between the latch circuits. The packet is processed by a logic circuit arranged between the latch circuits.
Referring to
FIG. 1
, a DDMP
240
employing the self-timed pipeline control scheme includes cascaded data latches
242
,
246
and
250
, logic circuits
244
and
248
arranged between these data latches
242
,
246
and
250
, and local handshake type data transfer control circuits (referred to as “C element” hereinafter)
260
,
262
and
264
cascade-connected to each other to effect data handshaking transfer between the data latches by transmitting/receiving a transmission signal SEND and a response signal ACK with respect to each other to apply a data latch timing signal to data latches
242
,
246
,
250
, and the like.
Thus, a data transfer circuit configuration formed of data latch circuits and C elements is provided in succession in DDMP
240
employing the self-timed pipeline control scheme. Data is transferred sequentially through a plurality of data latches and is subjected to a relevant process by an appropriate logic circuit arranged therebetween.
Reflecting the recent development in semiconductor equipment and digital signal processing technology, the market of equipment employing digital signal processing systems has seen rapid increase and change. Accordingly, the application field of DDMPs is also expanding.
The field of image processing and video signal processing that involves a great amount of operation processing occupies a relatively large portion in the DDMP application field. Particularly in the field of image processing that deals with television signals corresponding to a motion picture as well as still picture signals, there are many processes specific to each technical field. Many of these processes can be realized using a general purpose DDMP. In such a case, a function or the like that is not used in that particular technical field may be included in the DDMP. This induces the problem that the chip of the LSI is unnecessarily increased in size. Furthermore, the usage of a general purpose DDMP impedes increase of the processing speed and reduction of power consumption. Such various technical problems are encountered.
In view of the above-described problems, there is the growing demand for an LSI chip realizing a DDMP of a particular specification from users. The need arises for manufacturers to establish the technology of designing various types of custom LSIs optimized to each of such special specifications.
To this end, an LSI with a DDMP was generally designed using a bottom up design procedure or a top down design procedure.
The design flow in designing an LSI using the bottom up design procedure will be schematically described with reference to FIG.
2
. In the bottom up design procedure, first an LSI specification is provided (
280
). The LSI specification specifies the operation performance indicated by the processing amount per unit time required for the LSI, the total memory capacitance, architecture, and the like.
The function/logic designing is carried out based on this LSI specification (
282
). Specifically, the structure of the megaengine, macroprocessor, router, nanoprocessor, functional block and the like as well as the format of the packets circulating therethrough are determined.
Then, gate level designing is carried out based on the obtained logic design result (
284
). In gate level designing, the logic design result is replaced manually with a gate level circuit that is required in the LSI design. Here, the gate level circuit refers to logic circuits such as an inversion logic element (inverter: INV), logical product element (AND), logical sum element (OR) and the like.
The obtained gate level design is verified through logic/timing simulation (
286
). The layout is designed using the verified net-list (
288
).
The design flow of designing an LSI using the top down design procedure will be described with reference to FIG.
3
. Similar to the bottom up design procedure, an LSI specification is first provided (
300
). The function/logic design is implemented based on the applied LSI specification (
302
).
The function of this level is described manually at the register transfer level (RTL) using a function description language for use with LSI designing (Verilog-HDL (Hardware Description Language), VHDL (VHSIC Hardware Description Language) and the like) (
310
). Then, an RTL simulation is run to verify the function at this level (
312
). The function description verified by the RTL simulation is net-listed using a logic synthesis tool (
314
).
A logic/timing simulation is run with respect to the obtained net-list (
316
). The layout is designed using the verified net-list (
318
).
In the bottom up design procedure, manual work is required at the stage of gate level designing. In the top down design procedure, manual work is required at the RTL description stage. In either case, manual work is required every time in designing. The required labor of the manual work was not so noticeable when the number of gates included in the LSI was relatively small. However, the manpower and time required for designing has increased significantly lately since as many as several hundred thousand to several million gates are accommodated in one LSI. Accordingly, the designing cost will increase. Furthermore, as the specification is diversified, designing corresponding to each type must be implemented. It was therefore difficult to effectively utilize the currently available design resource.
In either case of using the conventional bottom up designing procedure or top down designing procedure, extensive resource must be invested in the development of a processor LSI using a self-timed data driven processor (custom DDMP LSI) that is optimized (customized) for each of the manifold applications. In other words, there are the disadvantages such as more manpower required for designing and a longer designing period. Accordingly, the designing cost will become higher. Since it is difficult to effectively utilize the currently-available design resource, the designing cost cannot be easily reduced.
There is also the problem that the number of elements to be determined acco
Uratani Munehiro
Yumoto Manabu
Birch & Stewart Kolasch & Birch, LLP
Nelms David
Pham Ly Duy
Sharp Kabushiki Kaisha
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