Parallelized cyclical redundancy check method

Details Parallelized cyclical redundancy check method Parallelized cyclical redundancy check method

1996-09-11

1999-01-19

Gordon, Paul P.

Excavating

371 3707, 371 376, G06F 1110

Patent

active

058621598

ABSTRACT:
A method for encoding information bits to derive a cyclically encoded group of code bits from the information bits that were encoded, using a computer processor. A sequence of data states are generated that are the result of a series of exclusive OR operations of each of the code bits with each of the bits of a first generator word and bitwise ANDing each of the resultant bits with the results of the next previous such exclusive OR operations shifted in the direction of the least significant bit ("LSB") so as to generate a data state. The invention involves the following steps. First, an initial data state of zero is provided. Next, the LSB of the code bits is bitwise exclusive ORed with the current data state. Next, the result of the previous step is bitwise ANDed with the value n, where n is a selected binary value 2.sup.x -1, where x is any positive integer. Next, the current data state is changed to the next sequential data state by changing the data state to one of 2.sup.x predetermined data states, depending on the x LSBs of the result of the previous step. Then, both the code bits and the now current data state are shifted by x bits in the direction of the LSB; and, finally, the second through fifth of the foregoing steps are repeated until all code bits have been operated on.

REFERENCES:
patent: 5068859 (1991-11-01), Collins et al.
patent: 5612974 (1997-03-01), Astrachan
decaluse et al., "Interprocessor Communication in Synchronous Multiprocessor Digital Signal Processing Chips", IEEE, pp. 1816-1828, Dec. 1989.
Tozawa et al., "Low Cycle Skipping Rte SDP Modem For Every Small Earth Stations", IEEE, pp. 1100-1104, 1989.

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