Parallelization of resynthesis

Details Parallelization of resynthesis Parallelization of resynthesis

2001-04-25

2002-10-22

Nguyen, Cuong Quang (Department: 2811)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06470487

ABSTRACT:

FIELD
This invention relates to the field of integrated circuit design. More particularly the invention relates to optimizing integrated circuit design using parallel processing for various optimization tasks.
BACKGROUND
Microelectronic integrated circuits consist of a large number of electronic components, in which individual logic devices or groups of logic devices are applied to the surface of a substrate, typically a silicon wafer. Placement of the components of the integrated circuit in optimum positions on the chip helps to reduce chip costs, processor delays, size and the like. Because the integrated circuits typically contain hundreds of thousands, if not millions of components, the task of optimizing the placement of components on a chip surface is typically not practical without the aid of computers.
Computer aided designs are effective to provide component location on the chip surface for minimizing interconnection distances, wire sizes, processing times and the like. The smallest functional unit placed on a chip surface is typically defined as a cell. A cell may be a single logic component of a larger logic tree or may be one or more logic trees. During the optimization process, different characteristics of the integrated circuit are tested to determine whether they meet the design criteria for the integrated circuit. If all of the tested characteristics of the integrated circuit meet all of the design criteria, then perhaps the design of the integrated circuit is not altered. More commonly, however, the characteristics of the integrated circuit are tested and then the design of the integrated circuit is modified in some specific manner, in an iterative procedure called optimization that is intended to optimize at least a given set of the tested characteristics, as referenced against the design criteria. This iterative procedure is often referred to as a resynthesis of the integrated circuit.
Because of the large number of computations involved, the resynthesis procedure of an integrated circuit design can be a very lengthy process. What is needed, therefore, is a system whereby the resynthesis procedures can be accomplished in a shorter length of time.
SUMMARY
The above and other needs are met by a method for resynthesizing a design of an integrated circuit using a parallel processing mode. A single processing mode is entered by activating a main thread and locking a semaphore associated with the main thread. The design of the integrated circuit is resynthesized using the main thread. Tasks to be accomplished in the parallel processing mode are identified. The semaphore associated with the main thread is unlocked, and the operation of the single processing mode is ceased. Ordinal threads are activated by unlocking a semaphore associated with each ordinal thread. The tasks are processed in parallel by assigning the tasks to the ordinal threads and the main thread.
Upon completion of one of the assigned tasks by one of the ordinal threads, it is determined whether an additional task remains to be assigned. In the case where the additional task remains, the additional task is assigned to the completed one of the ordinal threads. In the case where the additional task does not remain, the completed one of the ordinal threads is inactivated. Upon inactivation of all of the ordinal threads, a return is made to the single processing mode, with the ordinal threads remaining inactive unless and until the main thread identifies more tasks to be accomplished in the parallel processing mode.
By use of the semaphores, the tasks performed in parallel by the main thread and the ordinal threads remain in synchronization, thus facilitating the application of parallel processing to the resynthesis procedure. The tasks preferably include local optimization of clusters, including computation of at least one of net capacities, wire delays, and cell delays.
According to other aspects of the invention, a computing apparatus and a program for implementing the method as described above are provided.


REFERENCES:
Combining Technology Mapping with Post-Placement Resynthesis for Performance Optimization Aiguo Lu et al. Institute of Electronic Design Automation Technical University of Munich IEEE Catalog No.: 98CB36273.*
Using Precomputation in Architecture and Logic Resynthesis Soha Hassoun et al. IEEE Catalog No.: 98CB35287.

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