Parallel write logic for multi-port memory arrays

Details Parallel write logic for multi-port memory arrays Parallel write logic for multi-port memory arrays

1996-02-23

1998-10-27

Zarabian, A.

Static information storage and retrieval

Addressing

Multiple port access

365156, G11C 800

Patent

active

058286233

ABSTRACT:
In a traditional multi-port memory, the writing of a memory cell is performed only by the single port which is enabled for writing. Row contention occurs when other ports access the same memory cell, such as when ports share the same row address, and when the other ports are reading previously-stored data of opposite polarity. A parallel write capability is disclosed which eliminates such row contention by using the other ports of a multi-port memory to assist in writing the memory cell. By forcing the other ports into a write of the same data there can be no contention. Whenever a read port accesses the same row as a write port, the read port's bitline corresponding to the selected column for the write port is also forced into a write of the write port's data, along with the write port's bitline corresponding to the selected column of the write port. The read port's data is unaffected regardless of whether the selected column for the read port differs from the selected column for the write port. Row contention is also eliminated when multiple ports simultaneously write. For example, when a first port writes a memory cell at a first column, any other port sharing the same row address is forced into a write state on that first column to assist in writing the first port's selected memory cell. If a second port writes a memory cell sharing the same row address but located at a second column, the first port is forced into a write on the second column to assist in writing the second port's selected memory cell. Even if a port is writing, it will assist any other port in writing that port's selected memory cell if there is row contention. The present invention advantageously allows use of a "4T" memory cell (having high value resistor loads) when the number of incorporated ports would previously have required the use of a "6T" memory cell. By using a "4T" memory cell, a much smaller die size is achievable. Moreover, since the write port never has to discharge bitlines associated with a read port through the memory cell access transistors, many of the write timing parameters are dramatically improved.

REFERENCES:
patent: 5477502 (1995-12-01), Hayashi
patent: 5481495 (1996-01-01), Henkels et al.
patent: 5561638 (1996-10-01), Gibson et al.
patent: 5629901 (1997-05-01), Ho
patent: 5646893 (1997-07-01), McMinn et al.

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