Parallel write logic for multi-port memory arrays

Details Parallel write logic for multi-port memory arrays Parallel write logic for multi-port memory arrays

1997-05-19

1999-11-09

Zarabian, A.

Static information storage and retrieval

Addressing

Multiple port access

365156, G11C 800

Patent

active

059826991

ABSTRACT:
In a traditional multi-port memory, the writing of a memory cell is performed only by the single port which is enabled for writing. Row contention occurs when other ports access the same memory cell, such as when ports share the same row address, and when the other ports are reading previously-stored data of opposite polarity. A parallel write capability is disclosed which eliminates such row contention by using the other ports of a multi-port memory to assist in writing the memory cell. By forcing the other ports into a write of the same data there can be no contention. Whenever a read port accesses the same row as a write port, the read port's bitline corresponding to the selected column for the write port is also forced into a write of the write port's data, along with the write port's bitline corresponding to the selected column of the write port. The read port's data is unaffected regardless of whether the selected column for the read port differs from the selected column for the write port. Row contention is also eliminated when multiple ports simultaneously write.

REFERENCES:
patent: 5335199 (1994-08-01), Aoyama
patent: 5477502 (1995-12-01), Hayashi
patent: 5481495 (1996-01-01), Henkels
patent: 5561638 (1996-10-01), Gibson
patent: 5629901 (1997-05-01), Ho
patent: 5646893 (1997-07-01), McMinn

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