Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-05-01
2004-06-29
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S780000, C714S792000, C714S796000
Reexamination Certificate
active
06757859
ABSTRACT:
FIELD OF INVENTION
This invention relates to the field of digital communications, and in particular to an encoder and decoder for use in the implementation of a turbo trellis-coded modulation scheme.
BACKGROUND OF THE INVENTION
Turbo code has attracted a lot of interest due to its larger coding gain. See for example, “Application of Turbo Codes for Discrete Multi-Tone Modulation”, Hamid R. Sadjapour, AT&T Shannon Labs., 1996. Turbo code consists of two or more convolutional constituent codes separated by an interleaver acting on the input sequence of the first encoder. In a digital subscriber loop (DSL) system, Turbo code can be used to replace trellis code to get better Bit-Error Rate (BER) performance. However, when the constellation size increases, the coding gain advantage of turbo code starts to reduce. This is because the redundant bits makes the constellation size even larger.
SUMMARY OF THE INVENTION
According to the present invention there is provided encoding apparatus generating a turbo trellis code modulation signal, comprising an encoder data block for storing incoming data, and at least two recursive systematic convolutional encoders, said convolutional encoders being connected to receive data in parallel from said encoder data block.
The described parallel implementation structure reduces the implementation cycle for both encoder and decoder. Also, the memory (RAM) requirement for the turbo decoder can also be saved by ⅓ in the case of a three bit parallel implementation.
The invention also provides decoding apparatus for a turbo coded trellis code modulation signal, comprising a pair of decoders performing forward and backward iteration on an input signal, and interleaver and de-interleaver, each decoder taking at n soft bit inputs for each turbo decoder iteration, where n is an integer greater than 1.
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(Marks & Clerk)
Baker Stephen M.
Zarlink Semiconductor Inc.
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