Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2001-12-05
2003-02-11
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S155000
Reexamination Certificate
active
06518905
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to analog to digital converters, and in is particular to analog to digital converters comprising a parallel, time-interleaved delta sigma modulator architecture.
Digital circuitry has become increasingly prevalent in a wide variety of electronic devices including telecommunications, audio, video, portable/mobile communication transmitters and receivers, and other consumer products. One reason for the popularity of digital circuitry is that digital signal processing can be used to replace large numbers of analog components. Eliminating analog components from a device can lead to a reduction in the size, weight, and power requirements, while increasing flexibility and reliability of the device.
Analog-to-digital converters (ADCS) provide a link between the analog and digital domains. The ADC must be capable of converting analog data to digital data in an accurate manner, appropriate to the bandwidth and resolution needs of a given application. One type of ADC that is commonly used for analog to digital conversion is the oversampling ADC based on delta sigma (&Dgr;&Sgr;) modulation. Oversampling ADCs are used in applications requiring high-resolution analog to digital conversion because this approach permits high resolution without the need for extremely tight tolerances for analog components. &Dgr;&Sgr; modulation may be implemented using a mix of analog and digital circuitry, and is comprised generally of an input sampler, a filter, a quantizer, and a feedback path to sum the quantizer output back into the input to the filter. The quantizer output signal also defines the &Dgr;&Sgr; modulator output signal. A clock signal supplied to the &Dgr;&Sgr; modulator determines the sampling frequency, or the frequency at which the modulator output is updated.
Oversampling ADCs use an oversampling ratio (OSR) that is the ratio of the sampling frequency of the &Dgr;&Sgr; modulator to twice the bandwidth (Nyquist Frequency) of the input signal. The oversampling ratio is typically greater than one, and is often twenty-five or more. For conventional first order &Dgr;&Sgr; modulators, the signal to quantization noise (S/N) ratio increases by approximately 9db (1.5 bits) for each doubling of the OSR. Thus, better resolution is achieved by implementing a higher OSR, that is, by using a sampling frequency that is much higher than the Nyquist Frequency. However, circuit components that operate at higher frequencies are difficult to realize and if realizable, cost more than those that operate at lower frequencies.
For example, when designing mixed signal circuits based upon clocked systems, the maximum clock frequency is usually determined by the slowest component in the system. In &Dgr;&Sgr; modulation circuits, it is usually the settling of the key analog component of the modulator that takes the longest time, and thus the bandwidth of an analog signal converted to digital information by a delta sigma modulator is limited by the maximum achievable clocking rate of the modulator.
Accordingly, despite the advantages of &Dgr;&Sgr; modulation ADC circuits, the need to oversample the input signal by the modulator renders &Dgr;&Sgr; modulation impractical for certain higher frequency applications. Many applications require a bandpass ADC, where the analog input signal frequency is centered at a high frequency and confined to some bandwidth. For example, the trend in modern receiver design is to move the analog-to-digital interface as close as possible to the antenna or sensor. Having the analog-to-digital conversion closer to the antenna in the signal path (higher frequency) eliminates multiple stages of down conversion to lower frequencies and the associated components such as analog filtering. However, moving the analog to digital interface to higher frequencies requires bandpass ADCs with high center frequencies and good resolution. The center frequencies may range from hundreds of Megahertz to tens of Gigahertz with bandwidths that are relatively small compared to the center frequencies.
Accordingly, there is a need for bandpass &Dgr;&Sgr; modulation analog to digital conversion circuits that are capable of converting analog signals having very high center frequencies and having high resolution within a given bandwidth.
SUMMARY OF THE INVENTION
The present invention overcomes the disadvantages of previously known delta sigma analog to digital converters by providing a time-interleaved delta sigma modulator architecture that allows the conversion of relatively high frequency signals with a relatively low sample frequency.
In accordance with one embodiment of the present invention, a bandpass time interleaved delta sigma modulator analog to digital conversion architecture comprises an analog input signal that is coupled in parallel, to a plurality of modulators. The output of each modulator is coupled to a respective input of a multiplexer, and the multiplexer output is coupled to a bandpass filter and decimation circuitry to provide the analog to digital conversion circuit output. Each modulator is clocked by a signal that operates at a predetermined sample frequency, and is time phase shifted such that each modulator samples the analog input signal in a time-interleaved manner. Also, the multiplexer includes an input control that is synchronized with the various time-interleaved clock signals such that the output of the multiplexer is updated to reflect the output of each of the plurality of modulators once per cycle of the sample frequency.
For example, M single channel delta sigma modulators having N-bit quantizer outputs are arranged in a parallel configuration and operated at a predetermined sample frequency (f
s
). The modulator outputs are time interleaved and digitally combined in a manner that provides performance characteristics comparable to a modulator with a sample frequency of Mf
s
. Thus, bandpass center frequencies that are much higher than conventional single channel architectures are achievable. Typical single channel first order modulator bandpass center frequencies are restricted to f
c
=f
s
/4. However, the present invention supports a range of center frequencies approaching Mf
s
/2. This increased frequency capability is obtained while maintaining the delta sigma noise shaping near the higher bandpass center frequencies to reduce the effects of quantization noise. This results in a high signal to noise ratio with a corresponding high resolution at the much higher center frequencies.
Accordingly, it is an object of the present invention to provide a delta sigma modulator analog to digital converter architecture that allows the conversion of relatively high frequency signals with a relatively low sample frequency clock.
It is an object of the present invention to provide a bandpass delta sigma modulator analog to digital conversion architecture that can convert signals having an increased center frequency over single delta sigma modulator architectures.
Other objects of the present invention will be apparent in light of the description of the invention embodied herein.
REFERENCES:
patent: 5392042 (1995-02-01), Pellon
patent: 5406283 (1995-04-01), Leung
patent: 5598159 (1997-01-01), Hein
patent: 5621408 (1997-04-01), Cake
patent: 5646621 (1997-07-01), Cabler et al.
patent: 5682161 (1997-10-01), Ribner et al.
patent: 5734683 (1998-03-01), Hulkko et al.
patent: 5757300 (1998-05-01), Koilpillai et al.
patent: 5907299 (1999-05-01), Green et al.
patent: 5595031 (1999-11-01), Okuda et al.
patent: 6034629 (2000-03-01), Heo et al.
patent: 6061008 (2000-05-01), Abbey
patent: 6107947 (2000-08-01), Lyden
patent: 6188345 (2001-02-01), McDonald et al.
patent: 6271782 (2001-08-01), Steensgaard-Madsen
patent: 6292121 (2001-09-01), Cake et al.
Killworth, Gottman Hagan & Schaeff LLP
Wright State University
Young Brian
LandOfFree
Parallel time interleaved delta sigma modulator does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Parallel time interleaved delta sigma modulator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel time interleaved delta sigma modulator will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3139022