Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2006-10-23
2009-08-25
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Read/write circuit
Testing
C365S185220, C365S185140
Reexamination Certificate
active
07580302
ABSTRACT:
A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.
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Chang Chin Hung
Chang Kuen-Long
Ho Wen Chiao
Hung Chun Hsiung
Liu Cheng-Chi
Haynes Beffel & Wolfeld LLP
Ho Hoai V
Lappas Jason
Macronix International Co. Ltd.
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