Parallel TESTMODE

Details Parallel TESTMODE Parallel TESTMODE

1993-08-06

1995-01-17

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

36518905, 371 211, G11C 700

Patent

active

053831578

ABSTRACT:
A testing circuit for reading and writing a greater number of data bits in parallel during a single clock cycle than through I/O data pins in a memory device. The testing circuit comprises at least one data-in buffer, a plurality of write buffers coupled to the data-in buffer, a plurality of write buses corresponding with the plurality of write buffers and coupled therewith, a plurality of read buses to retrieve data from a plurality of memory cells, a plurality of output buffers corresponding in number with the plurality of read buses and coupled therewith and at least one output driver. Additionally, the method of testing memory basically comprises the steps of inputting at least one data bit having the predetermined polarity into the memory device in order to produce a plurality of data bits having the predetermined polarity. These plurality of data bits are written in parallel into a plurality of memory cells. Thereafter, the plurality of data bits stored in the plurality of memory cells are retrieved and compared with the predetermined polarity to uncover any memory cell errors.

REFERENCES:
patent: 4860259 (1989-08-01), Tobita
patent: 4873669 (1989-10-01), Furutani et al.

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