Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-07-25
2001-10-09
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S233100
Reexamination Certificate
active
06301166
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a parallel test therefor and, more specifically, to a semiconductor memory device and a structure of a parallel tester for performing test of semiconductor memory devices at a high speed.
2. Description of the Background Art
As memory capacity of a semiconductor memory device, specially of a dynamic type RAM (hereinafter referred to as a DRAM) has been increased, time necessary for testing the semiconductor memory device has been remarkably increased.
The reason why this problem occurs is that the more the storage capacity of the semiconductor memory device, the larger the number of word lines included therein, and therefore the longer becomes the time for writing and reading memory cell information while successively selecting the word lines.
The aforementioned problem is more serious in an acceleration test such as a burn in test. In the burn in test, a semiconductor memory device is operated under a high temperature and high voltage condition in order to reveal potential initial failure such as defect in gate insulating film of an MOS transistor, which is a component of the device, defect in an interlayer insulating film between interconnections, defect in interconnection and defect caused by particles introduced during the steps of manufacturing, and to eliminate defective products before shipment.
The above described burn in test is essential in maintaining quality of the products to be shipped. The increase in time for the test is directly related to increase of manufacturing cost of the semiconductor memory device.
The problem of longer test time is also experienced in a reliability test such as a life test.
FIG. 45
schematically shows a structure of a conventional apparatus for performing burn in test.
Referring to
FIG. 45
, on a test board TB, semiconductor memory devices DR
11
to DRmn are arranged in a matrix of m rows x n columns. The semiconductor memory devices DR
11
to DRmn are connected to each other by a signal bus SG.
During testing, a control signal and a clock signal are output to test board TB from a test signal generating circuit TA. The control signal and the clock signal are transmitted to each semiconductor memory device by the signal bus SG.
In the burn in test, first, data at a high level is written to each memory cell of the semiconductor memory devices DR
11
to DRmn. Thereafter, a row address strobe signal /RAS and an address signal are applied from test signal generating circuit TA to signal bus SG, and in semiconductor memory devices DR
11
to DRmn, a word line is selected and sense amplifier circuit operates. The memory cell information amplified by the sense amplifier circuit is compared with the test data written in advance, and thus malfunction of each semiconductor memory device is detected.
The above described operation is continuously carried out for a prescribed time period under prescribed accelerating conditions.
FIG. 47
schematically shows a whole structure of a conventional dynamic semiconductor memory device. Referring to
FIG. 47
, the dynamic semiconductor memory device
1
includes a control circuit
18
receiving external control signals /WE, /OE, /RAS and /CAS applied through external control signal input terminals
2
to
5
for generating internal control signals; a memory cell array
7
in which memory cells are arranged in a matrix; an address buffer
9
receiving external address signals AO to Ai applied through an address signal input terminal
8
for generating an internal row address signal and an internal column address signal under the control of the control circuit
18
; an internal address generating circuit
10
for generating a refresh row address signal for designating a row to be refreshed during refreshing operation under the control of control circuit
18
; a multiplexer
11
for selectively passing any of the address signals from address buffer
9
and internal address generating circuit
10
under the control of control circuit
18
; and a row decoder
12
which is activated under the control of control circuit
18
for decoding the internal row address signal applied from multiplexer
11
to select a row of the memory cell array
7
.
The signal /WE applied to external control signal input terminal
2
is a write enable signal designating data writing. The signal /OE applied to external control signal input terminal
3
is an output enable signal designating data output. The signal /RAS applied to the external control signal input terminal
4
is a row address strobe signal for starting internal operation in the semiconductor memory device and for determining active time period of the internal operation.
While the signal /RAS is active, circuits related to an operation of selecting a row in the memory cell array
7
are activated. The signal /CAS applied to external control signal input terminal
5
is a column address strobe signal, which activates a circuit for selecting a column in memory cell array
7
.
Semiconductor memory device
1
further includes a column decoder
13
which is activated under the control of control circuit
18
for decoding an internal column address signal from address buffer
9
and generating a column selecting signal for selecting a column of the memory cell array
7
; a sense amplifier sensing and amplifying data of a memory cell connected to the selected row of the memory array
7
; an IO gate responsive to a column selection signal from column decoder
13
for connecting the selected column of the memory cell array
7
to an internal data bus a
1
; an input buffer
15
for generating an internal write data from external write data DQ
0
to DQj applied to data input terminal
17
at the time of data writing and transmitting thus generated data to internal data bus a
1
, under the control of control circuit
18
; and an output buffer
16
for generating external read data DQ
0
to DQj from internal read data read to internal data bus a
1
at the time of data reading and outputting thus generated read data to data input/output terminal
17
, under the control of control circuit
6
.
Referring to
FIG. 47
, the sense amplifier and the IO gate are represented by one block
14
. Input buffer
15
is activated when the signals /WE and /CAS are both at the active state of low level and generates the internal write data. Output buffer
16
is activated in response to the activation of the output enable signal /OE.
As described above, the operation of the DRAM is controlled by the aforementioned external signals /WE, /OE, /RAS and /CAS as well as address signals A
0
to Ai.
Therefore, even in the burn in test, these signals are applied from test signal generating circuit TA to each of the semiconductor memory devices DR
11
to DRmn.
In the above described burn in test, in order to suppress increase in test time even when the memory capacity of each semiconductor memory device is increased, the control signal /RAS transmitted from test signal generating circuit TA to signal bus SG shown in
FIG. 45
may be changed at high speed, so as-to shorten the time necessary for the word line to be selected.
However, a large number of semiconductor memory devices DR
11
to DRmn are connected to signal bus SG, and there is a large parasitic capacitance Cp at signal bus SG, as shown in FIG.
45
. Therefore, because of interconnection resistance and the large parasitic capacitance of the signal bus SG, there is a signal propagation delay, and hence increase in speed of changing said signal is limited.
FIG. 46
shows the change in the control signal /RAS and of the address signal on signal bus SG, as an example.
FIG.
46
(A) shows an ideal signal waveform on signal bus SG, and FIG.
46
(B) shows a signal waveform on signal bus SG in the conventional burn in test. As shown in FIG.
46
(A), in the ideal state, the signal /RAS changes with a prescribed rise time and a prescribed fall time, not influenced by the signal propagation delay. The address signal requires a set up time Ts
Ho Hoai V.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Parallel tester capable of high speed plural parallel test does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Parallel tester capable of high speed plural parallel test, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parallel tester capable of high speed plural parallel test will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2553158