Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2002-11-26
2003-12-09
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
06662315
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory devices, and, in particular, those devices which employ parallel test features.
BACKGROUND
Conventional memory devices, for example static random access memories (SRAMs) and dynamic random access memories (DRAMs), as are commonly used in computer systems, often include parallel test features. Such features allow a manufacturer to test the memory cells of the device more quickly. In general, each cell of the memory device is tested to determine whether it is functioning properly (i.e., whether it is properly retaining a stored state). For large memories (e.g., on the order of 1 Megabit or more), parallel testing allows multiple cells (or bits) of the memory to be tested at the same time. For example, instead of having to test each cell individually, parallel test features incorporated into the memory or other programmable device may allow a manufacturer to test four, eight, sixteen, etc. cells at a time, thus reducing the overall test time for the device (a factor which has been recognized as being a significant portion of the overall production costs of a memory device).
Although such “functional” (e.g., pass/fail) parallel testing for memory devices has been available (see, e.g., U.S. Pat. No. 5,383,157 entitled Parallel Testmode, assigned to the assignee of the present invention, the entire disclosure of which is incorporated herein by reference), such testing often provides no indication of the so-called critical path timing of the device under test in the case of an asynchronous memory. The “critical path” is the path through the device which determines the access time. For synchronous memory devices, the presence of input and output registers that are under the control of a common clock signal tends to set the timing parameters rather than the performance of any test circuitry. To illustrate, consider the synchronous memory
10
shown in FIG.
1
. Input data
12
is applied to the input port of an input register
14
and is latched in the input register
14
in response to a clock signal
16
. The data from input register
14
is written to a number of selected cells (e.g., four cells) of memory core
18
and the selected cells are programmed to retain the state of the data in signal
12
. To test the functionality of the selected cells, the state of these cells is read by output register/test circuit
20
in response to a subsequent clock signal
16
. Output register/test circuit
20
determines whether the state of each of the cells agrees with the state of the input data signal
12
and provides an indication of same as data out signal
22
. Thus, data out signal
22
provides an indication as to whether there were any functional failures of the selected cells of memory core
18
.
The signals from memory core
18
are latched in output register/test circuit
20
in response to clock signal
16
before they are tested. Thus, even the slowest of these signals has a predetermined time to set up before it is tested. Any timing differences between these signals is effectively masked by clock signal
16
. Thus it can be seen that it is possible to easily add test circuitry to synchronous memories without impacting access, or clock to data output, time. In the case of asynchronous memories, the test circuitry itself must be configured to ensure that critical path timing is unaffected when test modes are invoked.
In a related and application entitled “Parallel Test For Asynchronous Memory”, application Ser. No. 08/985,890, filed Dec. 5, 1997, by James Allen, John Silver and Keith Ford and assigned to the Assignee of the present invention, the complete disclosure of which is hereby incorporated by reference, an asynchronous memory with parallel test circuitry configured to provide a measure of a slowest bit access time for the device was described. This parallel test circuitry included first circuitry configured to receive logic signals from a plurality of memory cells and to provide first output signals indicative of logic states of the plurality of those cells. The parallel test circuitry also included second circuitry configured to receive the first output signals and to produce second output signals indicative of logic states of the first output signals therefrom. In one example, such parallel test circuitry was configured for use in the read path of the memory device, thus allowing the second output signals to be produced at the slowest bit access time.
FIG. 2
illustrates an asynchronous memory device
50
configured in accordance with the invention described in the above-cited co-pending application. Memory
50
is configured with parallel test circuitry which, as indicated above, can significantly reduce the time required to test the memory cells thereof and provide a measure of the access time of a slowest cell or bit. For this embodiment, memory
50
includes a memory core
52
arranged as North and South blocks, each block having a Far and a Middle quarter. Thus, memory core
52
includes Far North quarter
54
, Middle North quarter
56
, Middle South quarter
58
and Far South quarter
60
. Also included in memory core
52
are North and South redundant blocks
62
and
64
, respectively. North and South redundant blocks
62
and
64
(which may be arranged as redundant rows and/or columns) include memory cells which may be used to replace defective memory cells located in other quarters of memory core
52
. Although not shown in individual detail, it should be appreciated that memory core
52
is made up of a number of individual memory cells, which may be conventional SRAM cells.
During a parallel test operation, test data is written to selected cells of memory core
52
by simultaneously activating multiple memory blocks, for example as described in U.S. Pat. No. 5,383,157. The data stored in these selected cells is read out and compared to the expected state as applied by the tester. This provides the functional test of the cells.
The parallel test circuitry for accomplishing the parallel test includes Far-Middle Multiplexers (FM MUX)
66
a
-
66
d
and North-South Multiplexers (NS MUX)
68
a
-
68
b
. In this context, the term multiplexer is used to describe the actions of the FM MUXs
66
a
-
66
d
which receive logic signals from selected cells of respective quarters of memory core
52
and provide output signals indicative of the logic states of these cells. For example, FM MUX
66
a
may receive logic signal LQFN from a selected cell within Far-North quarter
54
and logic signal LQMN from a selected cell within Middle-North quarter
56
. The logic complements of these signals (e.g., {overscore (LQFN)} and {overscore (LQMN)}) are received by FM MUX
66
c
. Logic signals LQFN and {overscore (LQFN)} correspond to the true and complement states of a selected memory cell within Far-North quarter
54
(e.g., as may be provided to true and complement bit lines coupled to a conventional SRAM cell). Similarly, logic signals LQMN and {overscore (LQMN)} correspond to the true and complement states of a selected cell in Middle-North quarter
56
. Thus, each FM MUX
66
a
and
66
c
receives true or complement, respectively, logic signals from selected cells of Far- and Middle-North quarters
54
and
56
.
Because the same data is written to the selected cells of Far- and Middle-North quarters
54
and
56
, the logic states of signals LQFN and LQMN should be the same when read by FM MUX
66
a
. That is, if a logic “1” is written to the selected cells, signals LQFN and LQMN should both indicate that a “1” was stored in the selected cells when these signals are read by FM MUX
66
a
(at least if these selected cells are functioning properly). Similarly, the logic states of signals {overscore (LQFN)} and {overscore (LQMN)} should be the same when read by FM MUX
66
c
. The output signals GQN and {overscore (GQN)} produced by FM MUX
66
a
and
66
c
, respectively, are indicative of the logic states of the selected cells which provided logic signal pairs LQFN/{overscore (LQFN)} and LQMN/{overscore (LQMN)}.
In a
Ford Keith A.
Gradinariu Iulian C.
Mulholland Sean B.
Silver John J.
Baderman Scott
Cypress Semiconductor Corporation
Wagner , Murabito & Hao LLP
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