Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-08-15
2001-11-27
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189020, C365S189080
Reexamination Certificate
active
06324107
ABSTRACT:
BACKGROUND
Conventional memory devices, for example static random access memories (SRAMs) and dynamic random access memories (DRAMs), as are commonly used in computer systems, often include parallel test features. Such features allow a manufacturer to test the memory cells of the device more quickly. In general, each cell of the memory device is tested to determine whether it is functioning properly (i.e., whether it is properly retaining a stored state). For large memories (e.g., on the order of 1 Megabit or more), parallel testing allows multiple cells (or bits) of the memory to be tested at the same time. For example, instead of having to test each cell individually, parallel test features incorporated into the memory or other programmable device may allow a manufacturer to test four, eight, sixteen, etc. cells at a time, thus reducing the overall test time for the device (a factor which has been recognized as being a significant portion of the overall production costs of a memory device).
Although such “functional” (e.g., pass/fail) parallel testing for memory devices has been available (see, e.g., U.S. Pat. No. 5,383,157 entitled Parallel Testmode, assigned to the assignee of the present invention, the entire disclosure of which is incorporated herein by reference), such testing provides no indication of the so-called critical path timing of the device under test in the case of an asynchronous memory. The “critical path” is the path through the device which determines the access time. For synchronous memory devices, the presence of input and output registers that are under the control of a common clock signal tends to set the timing parameters rather than the performance of any test circuitry. To illustrate, consider the synchronous memory
10
shown in FIG.
1
. Input data
12
is applied to the input port of an input register
14
and is latched to the input register
14
in response to a clock signal
16
. The data from input register
14
is written to a number of selected cells (e.g., four cells) of memory core
18
and the selected cells are programmed to retain the state of the data in signal
12
. To test the functionality of the selected cells, the state of these cells is read by output register/test circuit
20
in response to a subsequent clock signal
16
. Output register/test circuit
20
determines whether the state of each of the cells agrees with the state of the input data signal
12
and provides an indication of same as data out signal
22
. Thus, data out signal
22
provides an indication as to whether there were any functional failures of the selected cells of memory core
18
.
The signals from memory core
18
are latched in output register/test circuit
20
in response to clock signal
16
before they are tested. Thus, even the slowest of these signals has a predetermined time to set up before it is tested. Any timing differences between these signals is effectively masked by clock signal
16
. Thus it can be seen that it is possible to easily add test circuitry to synchronous memories without impacting access, or clock to data output, time. In the case of asynchronous memories, the test circuitry itself must be configured to ensure that critical path timing is unaffected when test modes are invoked.
SUMMARY OF THE INVENTION
In one embodiment, the present invention provides an asynchronous memory with parallel test circuitry configured to provide a measure of a slowest bit access time for the device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the device and to provide first output signals indicative of logic states of the plurality of cells. The parallel test circuitry may also include second circuitry configured to receive the first output signals and to produce second output signals indicative of logic states of the first output signals therefrom. In such an embodiment, the parallel test circuitry may be the same circuitry used in the read path of the memory device, and may be configured such that the second output signals are produced at the slowest bit access time.
The plurality of cells tested may include a single or multiple redundant cells of the device. Such redundancy is transparent to the test circuitry.
In addition, the parallel test circuitry may be configured such that the first circuitry includes one or more circuits, each of which includes first and second input paths from a number of the plurality of cells. First logic circuitry may be coupled to the first and second input paths, the first logic circuitry being configured to provide the first output signals. The second circuitry may include second logic circuitry configured to receive the first output signals and a test signal and to provide the second output signals.
In a further embodiment, the present invention provides a method including the steps of reading a plurality of cells of an asynchronous memory device in parallel and producing an output signal indicative of their logic state at the speed of the slowest cell access time.
REFERENCES:
patent: 6111800 (2000-08-01), Allan et al.
Allan James D.
Ford Keith A.
Silver John J.
Cypress Semiconductor Corporation
Elms Richard
Nguyen Hien
Wagner, Murabito & Hao L
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