Parallel test circuit for use in a semiconductor memory device

Details Parallel test circuit for use in a semiconductor memory device Parallel test circuit for use in a semiconductor memory device

1993-04-22

1995-11-28

Beausoliel, Jr., Robert W.

Excavating

371 211, 371 681, 365201, G01R 3128, G01R 3126, C11C 2900

Patent

active

054714800

ABSTRACT:
A parallel test circuit is provided in a semiconductor memory chip for use during both a wafer test and a package test. The parallel test circuit operates to automatically reduce the number of test output pins associated with a single package test to thereby increase the number of packages that can be tested simultaneously. The parallel test circuit includes a selector for limiting the number of output pads which may be activated during a package test run. The selector is responsive to a wafer test enable signal, from a selection control circuit, to control output pad selection.

REFERENCES:
patent: 4744061 (1988-05-01), Takemaew et al.
patent: 5072137 (1991-12-01), Slemmer
patent: 5072138 (1991-12-01), Slemmer et al.
patent: 5075892 (1991-12-01), Choy
patent: 5265100 (1993-11-01), McClure et al.
Prince, "Semiconductor Memories", A Handbook of Design, Manufacture, and Application, Second Edition, pp. 697-716.

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