Parallel test circuit for memory device

Details Parallel test circuit for memory device Parallel test circuit for memory device

1998-07-15

1999-04-06

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

36518905, 36518908, G11C 700, G11C 1604

Patent

active

058927212

ABSTRACT:
An parallel test circuit for memory device is provided. The parallel test circuit according to the present invention includes: a plurality of memory mats, wherein each of memory mats comprises a memory cell for writing two-bit data and an X, Y address decoder for accessing the memory cell; a amplifying unit having a plurality of main amplifiers, wherein each of main amplifiers compares and amplifies a voltage difference between two-bit data of corresponding memory cell, and thereby output one-bit logic value; a data reducing unit for reducing a plurality of logic value from the amplifying unit to one-bit logic value. Accordingly, the parallel test circuit according to the present invention improves test efficiency twice by which a single main amplifier compares and amplifies two-bit data.

REFERENCES:
patent: 5293386 (1994-03-01), Muhenthaler et al.
patent: 5301142 (1994-04-01), Suzuki et al.
patent: 5359561 (1994-10-01), Sakomura et al.

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