Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-09-13
2001-07-17
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S189040
Reexamination Certificate
active
06262928
ABSTRACT:
BACKGROUND INFORMATION
1. Field of the Invention
The present invention relates generally to the field of integrated circuits, and particularly Dynamic Random-Access Memories (DRAMs).
2. Description of Related Art
Networking companies are scrambling in a race to design and develop high performance network processing products for the terabit router market while reducing the cost to implement 10 giga-bits per second/OC192 and above optical carrier network interfaces. Terabit routers demand a fatter throughput of data packets for examining an incoming packet, retrieves a next hop location, and transfers the packet to destination. Memory chips serve as integral components in building a fast network infrastructure.
FIG. 1
is a circuit diagram illustrating a conventional parallel test mode circuit diagram. An odd memory cell
11
a
is coupled between sense amps
11
b
and sense amps
11
c
. Signals generated from sense amps
11
b
and
11
c
are coupled to a global parallel data bus
11
d
and a read/write control signal
11
e,
which further couples to a global parallel input/output (IO)
11
f.
Similarly, an even memory cell
12
a
is coupled between sense amps
12
b
and sense amps
12
c.
Signals generated from sense amps
12
b
and
12
c
are coupled to a global parallel data bus
12
d
and a read/write control signal
12
e,
which further couples to a global parallel IO
12
f.
A main IO
13
couples between global parallel IOs
11
e
and
12
e,
and multiple external IOs
14
a,
14
b,
14
c,
and
14
d.
A control circuit
15
receives RAS/CAS/read/write signal
16
and address inputs
17
for activating test signals
18
a
and
18
b
or read/write signal
11
e
and
12
e.
A shortcoming of this conventional circuit
10
is that there is limited number of IOs, which impose restrictions in expanding and tiling the number of IOs. The conventional circuit
10
also is not able to generate the disturbance test pattern in parallel for testing a neighboring memory cell.
Accordingly, it is desirable to have a DRAM circuit that efficiently performs parallel test of memory cells.
SUMMARY OF THE INVENTION
The present invention discloses a parallel test circuit and method for testing even bit line and odd bit line in a memory block simultaneously, preferably within the one clock cycle. The parallel test circuit comprises an even test circuit for testing an even bit line and an odd test circuit for testing an odd bit line. The parallel test circuit also includes a write circuit for writing data to a bit line, a read circuit including a data sense amp, an output buffer, and a comparator. Furthermore, the present invention provides the capability to conduct disturbance test in neighboring even and odd cells.
For example, in 16 bit lines, a write circuit writes the same data to each bit line. The comparator in the read circuit compares all 16 bits in the memory array to generate an output high when all data are identical, and generate an output low when data in of the bits fails to match with other bits in the memory array.
In one embodiment, the memory structure is implemented with a set of even sense amps from the bottom and a set of odd sense amps from the top, or vice versa. Consequently, this design advantageously places an even bit line adjacent to an odd bit line in opposite direction. Preferably, the even and odd bit lines hold different logic values, such as logic “0” in an even bit line and a logic “1” in an odd bit line. This structure provides the ability to determine the amount of interference or noise between the two adjacent even and odd bit lines. Additionally, since bits lines are connected to memory cells, the amount of interference or noise injected can be determined between adjacent memory cells.
Advantageously, the present invention enables the capability to test for interferences that are divided into even and odd bit line groups.
REFERENCES:
patent: 5400344 (1995-03-01), Mori
patent: 5610866 (1997-03-01), McClure
Kim Juhan
Wong Hing
Fernandez & Associates LLP
Nguyen Tan T.
Silicon Access Networks, Inc.
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