Parallel test board used in testing semiconductor memory...

Details Parallel test board used in testing semiconductor memory... Parallel test board used in testing semiconductor memory...

2002-03-08

2004-07-13

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB, C324S754090, C365S201000, C438S018000

Reexamination Certificate

active

06762615

ABSTRACT:

This application claims priority from Korean Patent Application No. 2001-12436, filed Mar. 10, 2001 and Korean Patent Application No. 2001-28955, filed May 25, 2001, the contents of which are incorporated herein by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to testing semiconductor memory devices, and more particularly, to a parallel test board used to test semiconductor memory devices in their actual operating environment.
2. Description of the Related Art
After completing the manufacturing process (circuit design, wafer fabrication, and packaging), but before shipment, semiconductor IC devices are typically subjected to a number of tests, including an electrical performance test, to verify their performance and reliability.
The electrical performance test may include a DC test, an AC test, and a functional test. The DC test is used to verify the DC characteristics of an IC device by performing an open/short test and by measuring input currents, output voltages, power supply currents, and so forth. The AC test measures the timing of an IC device by applying input pulse signals to input terminals of the device. The AC test checks the operational characteristics of the device such as the input/output propagation delay time (or access time), the start and finish times of input and output signals, and so forth. In the functional test, test patterns generated from a pattern generator are transformed into pulse signals of a normal level. The pulse signals are then applied to a Device Under Test (DUT). The output signals from the DUT are compared to reference signals. In the case of memory devices, for instance, this test is used to verify read/write functions and to determine mutual interference of each of the memory cells during actual operation. Generally, a dynamic functional test, which combines the functional and AC tests, is performed.
In mass-production, it is impossible to test memory devices under all of the operating conditions they will encounter in actual use. Furthermore, as the functions of the memory devices improve and as the fabrication processes for the devices become more complicated, the number of possible defect patterns and hence the time required for testing the devices each increase. It is therefore becoming more difficult to test for every possible defect. Even if a semiconductor device passes the functional and reliability tests, however, it might still have a defect that cannot be detected until after it is assembled into an electronic apparatus (e.g., a personal computer). In some cases, the manufacturers of these apparatuses have their own test programs to screen for defective memory devices that are not applicable to conventional memory test equipment or that require too much time to perform. Performing these tests when the memory device is manufactured would consequently impose a heavy time and cost burden on semiconductor memory producers.
Considering these technical problems, memory manufacturers have tried to adapt memory device testing technology to reproduce circumstances representative of the actual environment in which the memory devices will be used. When testing memory products such as Dual Inline Memory Modules (DIMMs), for example, it is necessary to create a test condition similar or equivalent to the environment under which the memory modules will actually be operated, such as in a main memory device of a personal computer. In its actual operating environment, the input/output functions of the memory module may be affected by peripheral devices of the computer system (e.g., CPU, sound cards, graphic card, and BIOS). Accordingly, in order to optimize the actual testing conditions of the memory modules, a motherboard is used as a test board. Test technologies that test the DUTs by mounting them onto a motherboard are referred to as “actual operational tests.”
FIG. 1
illustrates a conventional testing configuration for performing an actual operational test. As shown in
FIG. 1
, a parallel test board
20
is mounted onto a computer motherboard
10
.
FIG. 2
is a plan view of the parallel test board
20
shown in FIG.
1
.
Referring to
FIG. 1
, the motherboard
10
includes various electronic components such as module slots
12
. Absent the parallel test board
20
, memory module devices
27
to be tested would be mounted in the module slots
12
. A power terminal
13
is included to supply power to the motherboard
10
. The motherboard
10
further includes PCI slots
14
, IDE slots
15
, an I/O slot
16
(configured to input/output data to and from storage devices such as HDDs), an output terminal
17
(configured to be connected to external output devices such as a display), and a BIOS having built-in firmware.
The foregoing components are generally mounted on the front side (i.e., the top surface in
FIG. 1
) of the motherboard
10
, and are mutually or externally connected through soldering on the backside (i.e., the bottom surface in
FIG. 1
) of the board
10
. The module slots
12
are further electrically interconnected to the parallel test board
20
through soldering on the backside of the motherboard
10
. The parallel test board
20
is physically attached to the motherboard
10
using bolts attached through holes
19
of the motherboard
10
and holes
21
of the test board
20
. Memory modules
27
are mounted in the plurality of slots
22
,
23
,
25
.
Referring to
FIG. 2
, the conventional parallel test board
20
has three slots
22
,
23
,
25
that are configured to receive the memory modules to be tested. The use of a parallel test board
20
reduces the test time of the actual operational test. More particularly, the test time when memory devices are tested by directly mounting them in the module slots
12
of the motherboard
10
depends on the number of memory modules (i.e., the amount of memory). In that case, the memory module under test operates as a serial test module. As the memory capacity increases, therefore, the test time also increases. By providing a parallel test mode using the parallel test board
20
, multiple (in this case, three) memory modules can be tested in the same amount of time.
The parallel test board
20
includes a reference slot
25
that is directly connected to each of module slots
12
on the motherboard
10
. It also includes two parallel test slots
22
and
23
that have command signals connected in parallel with the reference slot
25
. According to this arrangement, the memory modules mounted in the reference slot
25
are driven directly by the motherboard
10
, while the memory modules mounted in the parallel test slots
22
,
23
are operated in parallel with the modules in the reference slot
25
. Accordingly, the memory modules loaded in the test slots
22
,
23
are tested simultaneously with the memory module loaded in the reference slot
25
. This results in a 67% reduction in test time.
Unfortunately, however, the actual environmental test using the parallel test board
20
suffers from several drawbacks. Among these disadvantages, a multi-bank operation failure cannot be detected using this test board arrangement. A multi-bank operation failure is when memory modules that have passed the conventional PC actual operational test fail when mounted in an actual PC motherboard. This failure can occur because two test slots
22
,
23
are connected in parallel with the reference slot
25
, which is directly connected to the motherboard
10
of the test device. In this configuration, the test results for the multiple modules in a conventional test are the same as if a single memory module is mounted to the motherboard. In other words, as long as at least one of the memory devices is not defective, no defect will appear. Defects in memory modules therefore cannot be accurately detected by the conventional actual operational test device and method in which a number of memory modules are mounted on the same system motherboard.
Additional drawbacks may also be present in the conventional actual operational te

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