Parallel terminated bus system

Details Parallel terminated bus system Parallel terminated bus system

2000-03-30

2003-02-11

Thai, Xuan M. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C710S305000

Reexamination Certificate

active

06519664

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention pertains to an apparatus and technique for operating a computer system. In particular, apparatus and techniques for controlling output buffer drive enable signals on a parallel terminated bus are described.
FIG. 1
is an example of a bi-directional parallel terminated bus system
10
. Drivers
12
have an impedance Z
o
and are operable to drive a signal on a bus
14
to receivers
16
. The bus
14
is terminated at each receiver
16
,
18
through a resistor R
1
between the bus and the source power supply Voltage V
s
and through a resistor R
2
between the bus and ground. The bus is therefore biased at a midpoint voltage when not driven by a driver
12
. Such a configuration makes the rise and fall times of signals on the bus symmetrical, which is desirable in a source synchronous environment. The parallel terminated bus may be unidirectional, bi-directional or multidirectional.
Any data exchange between drivers and receivers of two entities, such as between a processor and a memory device which may be on separate chips is typically accomplished in a synchronous manner. That is, the chips have internal clocks that are sufficiently in alignment with each other so that data may be acquired on clock signal transitions. In addition, data exchanges may be accomplished source-synchronously, which means that the exchanges are based on strobe signal transitions that have been derived from a clock signal and are synchronized to their corresponding data.
A parallel termination protocol has been developed to ensure correct data signal operation for two or more bus agents across a large operating range. A parallel termination protocol may also be suitable for use with other entities that drive and receive data in a parallel environment. In an implementation, the parallel termination protocol requires that a signal must be driven at all times to prevent a signal from floating to an unspecified logic level. If certain signals such as strobe signals were permitted to float, then the system would become unreliable. Such an occurrence may cause a fatal functional error in the system due to data transmission errors. To avoid such occurrences, the parallel terminated protocol may specify that a bus agent designated as the default bus master will synchronously time the drive cut-off points to occur when another bus agent would drive a signal onto the bus, for example, to return data requested by the bus master. The parallel terminated protocol may also specify that the default bus master is to source-synchronously latch the value on the bus, turn On its drivers, and drive the latched value back onto the bus on the arrival of the last strobe signal for the reply sent by the cache.
Although a parallel terminated protocol for high speed processor systems may readily be defined, a need exists for techniques and apparatus to implement the protocol over a wider range of operating frequencies with cleaner signal transitions.


REFERENCES:
patent: 5065397 (1991-11-01), Shiobara
patent: 5349610 (1994-09-01), Sakamoto et al.
patent: 5961649 (1999-10-01), Khandekar et al.
patent: 5964856 (1999-10-01), Wu et al.
patent: 6092212 (2000-07-01), Muljono et al.
patent: 6317801 (2001-11-01), Ilkbahar et al.

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