Parallel-stripe type semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S028000, C257S347000

Reexamination Certificate

active

06294818

ABSTRACT:

BACKGROUD OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with a large current capacity and a high breakdown voltage, such as a metal-oxide semiconductor field-effect transistor (MOSFET), an IGBT, a bipolar transistor, and semiconductor diode, and also the present invention relates to a method for fabricating the semiconductor device mentioned above.
2. Description of the Prior Art
In general, structures of the semiconductor elements can be roughly grouped into two types: a lateral structure having an electric contact portion on one side thereof; and a vertical structure having electric contact portions on both sides thereof.
One example of a semiconductor element with the lateral structure is a SOI (silicon on insulator) -MOSFET (metal oxide silicon field effect transistor) shown in FIG.
1
A and
FIG. 1B
, in which
FIG. 1A
is a plan view of the semiconductor element, while
FIG. 1B
is a cross-sectional view of the semiconductor along a line
1
B-
1
B′ in FIG.
1
A.
A structure of the SOI-MOSFET is based on an offset gate structure of an n-channel MOSFET, in which a p-type channel diffusion layer
7
, an n

-type low doped drain region (drain/drift region)
90
, and an n

-type drain region
9
are formed on a semiconductor base plate
5
via an insulation membrane
6
in that order. In addition, an n
+
-type source region
8
is formed on a part of a surface of the p-type channel diffusion layer
7
, and also an insulation layer
12
is formed on a region extending from an end portion of the region
8
to an end of the n
+
-type drain region
9
. Particularly, in close proximity to the above n
+
-type source region
8
, the insulating film
12
has a remainder portion
10
which is thinner than the rest of the insulating film and is positioned on the boundary of the p-type channel diffusion layer
7
and the n

-type low doped drain region
90
. A gate electrode
11
is formed so as to cover the insulation film
12
from its thin portion
10
to its thick portion.
The low doped drain region
90
can be operated as a drift region for transferring carriers due to the effect of an electrical field if the MOSFET is in the ON mode. If the low doped drain region
90
is in the OFF mode, on the other hand, it becomes a depletion region to reduce an electric field strength applied thereon, resulting in an increase in breakdown voltage. It is possible to reduce the drift resistance of the low doped drain region
90
by increasing the concentration of impurities in the low doped drain region
90
and by decreasing electricity flowing through the region
90
. As a result, a substantial ON resistance (drain-source resistance) of the MOSFET can be lowered. In this case, however, it will be difficult to extend the boundaries of the depletion layer between the drain and the channel to be developed from a P-N junction between the p-type channel diffusion layer
7
and the n-type low doped drain region
90
, so that the maximum permissible (critical) electric field strength of silicon is reached at an earlier time, resulting in a reduction in the breakdown voltage (drain-source voltage). Hence, a trade-off relationship exists between the ON resistance (current capacity) and the breakdown voltage. Similarly, it has been known that the semiconductors such as IGBT, bipolar transistors, and semiconductor diodes make the above trade-off relationship.
Referring now to
FIGS. 2A and 2B
, another example of the conventional MOSFETs having a lateral structure will be described in detail, in which
FIG. 2A
is a cross-sectional view of a p-channel MOSFET and
FIG. 2B
is a cross-sectional view of a double diffusion type n-channel MOSFET.
The p-channel MOSFET shown in
FIG. 2A
comprises a n-type channel diffusion layer
3
formed on a p-type semiconductor layer
4
, a gate electrode
11
with a field plate formed on the diffusion layer
3
via a gate insulation film
10
, a p
+
-type source region
18
formed on a part of the diffusion layer
3
in close proximity to one end of the gate electrode
11
, a p-type low doped drain region (drain/drift region)
14
formed as a well having an end immediately underneath the other end of the gate electrode
11
, a n
+
-type contact region
71
adjacent to the p-type source region
18
, a thick insulation film
12
formed on the p-type low doped drain region
14
. In this structure, therefore, its ON resistance and breakdown voltage can be defined as the trade-off relationship based on the amount of electricity flowing through the well-shaped p-type low doped drain region
14
and the concentration of its impurities.
The double diffusion type n-channel MOSFET shown in
FIG. 2B
comprises a n-type low doped drain layer (drain/drift layer)
22
formed on a p-type semiconductor layer
4
, a gate electrode
11
with a field plate formed on the low doped drain layer
22
via a gate insulation film
10
, a p-type channel diffusion region
17
formed on a part of the low doped drain layer
22
in close proximity to one end of the gate electrode
11
, n

-type source region
8
formed as a well in the p-type channel diffusion region
17
, an n
+
-type drain region
9
formed as a well positioned at a distance from the n
+
-type source region
8
and the gate electrode
11
, a well-shaped p-type top layer
24
formed on a surface layer between the gate electrode
11
and the n
+
-type drain region
9
, a p
+
-type contact region
72
adjacent to the n
+
-type source region
8
, and a thick insulation film
12
formed on the p-type top layer
24
. In this structure, therefore, its ON resistance and breakdown voltage can be defined as the trade-off relationship based on the amount of electricity flowing through the well-shaped n-type low doped drain region
22
and the concentration of its impurities.
In the structure of
FIG. 2B
, however, the n-type low doped drain layer
22
is sandwiched between the p-type semiconductor layer
4
and the p-type top layer
24
, so that it can be provided as the structure with a high breakdown voltage if the MOSFET is in the OFF mode because the low doped drain layer
22
is depleted at an earlier time by widening a depletion layer not only from the P-N junctions ja with the p-type channel diffusion region
17
but also from p-n junctions jb of upper and lower sides of the n-type low doped drain layer
22
while the concentration of impurities in the low doped drain layer
22
can be increased.
FIG. 3
shows a trench gate type n-channel MOSFET as an example of the vertical semiconductor element. The n-channel MOSFET comprises a n-type low doped drain layer
39
formed on a n
+
-type drain layer
29
electrically contacted with a back electrode (not shown), a trench gate electrode
21
imbedded in a trench formed on a surface of the low doped drain layer
39
via a gate insulation film
10
, a p-type channel diffusion layer
27
formed on a surface of the low doped drain layer
39
at a relatively shallow depth compared with that of the trench gate electrode
21
, a n
+
-type source region
18
formed along an upper edge of the trench gate electrode
21
, and a thick insulation film
12
as a sheathing of the gate electrode
21
. By the way, it is possible to make a n-type IGBT structure using a double structure made of a n

-type upper layer and a p
+
-type under layer instead of the single layered n
+
-drain layer
29
. In This kind of the vertical structure, therefore, the low doped drain layer
39
acts as a drift region for drift current flowing in the vertical direction if the MOSFET is in the ON mode, while it is depleted to increase its breakdown voltage if the MOSFET is in the OFF mode. In this case, its ON resistance and breakdown voltage can be defined as the trade-off relationship on the basis of a thickness of the low doped drain layer
39
and he concentration of its impurities.
FIG. 4
is a graph that shows the relationship between an ideal breakdown voltage a

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