Parallel signal automatic phase adjusting circuit

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C375S376000, C370S516000

Reexamination Certificate

active

07139347

ABSTRACT:
A parallel signal automatic phase adjusting circuit includes a signal generator for generating a signal having a predetermined frequency, an oscillating circuit for generating a clock signal having a frequency smaller than an inputted clock signal by the predetermined frequency, and adjusting circuits, respectively corresponding data signal channels, each adjusting the generated clock signal so as to be synchronized with the corresponding data signal, based on an arithmetic operation of trigonometric functions using both phase comparing information, derived from comparison between the corresponding data signal and the generated clock signal, and frequency information regarding the corresponding data signal, the generated clock signal and the signal from the signal generator. The circuit is useful, for example, when digital data transmitted through a large number of parallel data signal lines between data terminals, because the size of and the cost for the circuit are reduced.

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patent: 6363129 (2002-03-01), Agazzi
patent: 6526112 (2003-02-01), Lai
patent: 6552619 (2003-04-01), Shastri
patent: 6636993 (2003-10-01), Koyanagi et al.
patent: 6700942 (2004-03-01), Lai
patent: 6813724 (2004-11-01), Saito
patent: 2002/0009169 (2002-01-01), Watanabe
patent: 2002/0044618 (2002-04-01), Buchwald et al.
patent: 2002/0048335 (2002-04-01), Saeki

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