Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-12-05
2004-10-05
Thai, Xuan M. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S300000, C710S315000, C710S314000, C370S389000
Reexamination Certificate
active
06801975
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to parallel SCSI host adapters, and more particularly, to using a parallel SCSI host adapter with the Packetized SCSI Protocol.
2. Description of Related Art
A variety of parallel host adapter architectures is available. See for example, U.S. Pat. No. 5,655,147 or U.S. Pat. No. 5,659,690. Each parallel host adapter provides connectivity between two I/O buses, e.g., a SCSI bus to a host I/O bus such as a PCI bus.
A high-level block diagram of one prior art parallel SCSI host adapter
100
(
FIG. 1
) that had a channel architecture with an administrative information channel
101
and a data channel
102
.
Administrative information was transferred to and from host I/O bus
170
via administrative information channel
101
. Administrative information channel
101
coupled a sequencer control block (SCB) array memory
155
to PCI bus
110
. Specifically, in channel
101
, a command direct memory access (DMA) engine
115
coupled PCI bus
170
to SCB array memory
155
. SCB array memory
155
could be either memory onboard parallel host adapter
100
, or memory external to parallel host adapter
100
.
Data channel
102
coupled SCSI bus
180
to PCI bus
170
so that data could be transferred between the two I/O buses. A SCSI module
120
coupled SCSI bus
180
to a first-in-first-out (FIFO) data buffer
130
. SCSI module
120
transferred data on SCSI bus
180
to FIFO data buffer
130
, and transferred data from FIFO data buffer
130
to SCSI bus
180
.
A data DMA engine
113
, typically included in a host interface module
110
within parallel host adapter
100
, coupled FIFO data buffer
130
to PCI bus
170
. Data DMA engine
113
transferred data on PCI bus
170
to FIFO data buffer
130
, and transferred data from FIFO data buffer
130
to PCI bus
170
. As is known to those of skill in the art, DMA engines
115
and
113
were typically configured by an onboard sequencer
150
using administrative information in a sequencer control block stored in SCB array
155
that was addressed by the contents of SCB array pointer register
131
.
This prior art channel configuration allowed only one data context in the data channel at a time. As used here, data context means data transfers associated with a particular command, e.g., a particular SCB.
FIFO data buffer
130
was designed to minimize the time that parallel host adapter
100
required access to PCI bus
170
, and to accept data from SCSI bus
180
without introducing delay on SCSI bus
180
. For example, in a receive operation where data was transferred from SCSI bus
180
to PCI bus
170
, data from SCSI bus
180
was collected in FIFO data buffer
130
until there was sufficient data in FIFO data buffer
130
to justify requesting access to PCI bus
170
. Typically, data was burst to the host from FIFO data buffer
130
using the highest speed PCI transfer mode.
If for some reason, a transfer associated with a particular read context was stopped, the state data was transferred from DMA address/count registers
114
to the SCB in SCB array
155
by sequencer
150
when all the data was transferred from FIFO data buffer
130
. This typically required a wait while the data drained from FIFO data buffer
130
, which in turn affected performance.
The SPI-3 Packetized SCSI specification requires that the state of a data path be saved at the end of each data packet, referred to hereafter as a data information unit. A data information unit from target
172
may be followed by another data information unit of the same context, a data information unit of a different context, or some other SCSI bus phase not related to a data transfer.
At the end of a data information unit, host adapter
100
must save information about the data transfer that tells host adapter
100
where to resume the data transfer for another data information unit of the same context. This information was referred to above as the state of the data path.
Specifically, according to the Packetized SCSI Protocol the following must be saved:
the address of the host buffer to or from which data is to be transferred for the next data information unit of the same context, and
the number of data bytes remaining to be transferred.
When the data transfer is specified by a Scatter/Gather list, information must also be saved regarding the progress through the list. Using sequencer
150
to copy the state data to the SCB between each data information unit introduces a latency that seriously degrades the performance of the data transfers using the Packetized SCSI protocol.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention, a parallel SCSI host adapter includes a SCSI bus port and a host I/O bus port. The parallel SCSI host adapter takes a snapshot of state data for a first data channel coupling the SCSI bus port to the host I/O bus port following receipt of a complete Packetized SCSI protocol information unit having a context from the SCSI bus port. To take the snapshot, the state data is transferred from registers for the first data channel to corresponding registers for a second data channel. Following the snapshot, another Packetized SCSI protocol information unit for the same context is transferred over the first data channel. Since the snapshot requires substantially no time delay relative to a time delay associated with saving the state data in a hardware I/O command block for the context, latency between the information units for the same context can be eliminated in the parallel SCSI host adapter.
In one embodiment of the present invention, a parallel SCSI host adapter has a SCSI bus port and a host I/O bus port. The parallel SCSI host adapter includes a first data channel that in turn includes a first shadow register. The first data channel is selectably connected to the SCSI bus port to form a first data path between the SCSI bus port and the host I/O bus port.
The parallel SCSI host adapter, in this embodiment, further includes a second data channel that in turn includes a second shadow register coupled to the first shadow register. The second data channel is selectably connected to the SCSI bus port to form a second data path between the SCSI bus port and the host I/O bus port.
In addition, the parallel SCSI host adapter includes a first snapshot strobe line connected to the second shadow register. An active signal on the first snapshot strobe line causes content of the first shadow register to be loaded in the second shadow register. This content is one of (a) an address and (b) a count value. To capture both the address and the count value, shadow address/count registers are used.
The parallel SCSI host adapter, in one embodiment, further includes a second snapshot strobe line connected to the first shadow register. An active signal on the second snapshot strobe line causes content of the second shadow register to be loaded in the first shadow register.
The first data channel also includes a first hardware I/O command block array pointer register. Similarly, the second data channel also includes a second hardware I/O command block array pointer register connected to the first snapshot strobe line, and coupled to the first hardware I/O command block array pointer register. The active signal on the first snapshot strobe line causes content of the first hardware I/O command block array pointer register to be loaded in the second hardware I/O command block array pointer register.
The second snapshot strobe line is connected to the a first hardware I/O command block array pointer register so that the active signal on the second snapshot strobe line causes content of the second hardware I/O command block array pointer register to be loaded in the first hardware I/O command block array pointer register.
In another embodiment of this invention, a method includes transferring a Packetized SCSI protocol data information unit over a first data path of a first data channel coupling a SCSI port of a parallel SCSI host adapter to a host I/O port of the para
Adaptec, Inc.
Gunnison Forrest
Gunnison McKay & Hodgson, L.L.P.
King Justin
Thai Xuan M.
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