Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
2002-01-31
2004-09-21
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S535000, C345S537000, C345S557000
Reexamination Certificate
active
06795078
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of computer graphics and, more particularly, to memory controller architecture.
2. Description of the Related Art
With each new generation of graphics system, there is more image data to process and less time in which to process it. This consistent increase in data and data rates places additional burden on the memory systems that form an integral part of the graphics system. Attempts to further improve graphics system performance are now running up against the limitations of these memory systems in general, and memory device limitations in particular.
In order to provide memory systems with increased data handling rates and capacities, system architects may employ consistently higher levels of integration. One example of increased integration is the 3D-RAM family of memories manufactured by the Mitsubishi Corporation. A 3D-RAM memory may include multiple banks of DRAM main storage with level one and level two cache memories, and a bank-swapped shift register capable of providing an uninterrupted stream of sequential data at current pixel clock speeds.
In graphics applications, it is often necessary or desirable to read data (or a stream of data) from a source buffer, to transfer the data to a destination buffer, and to clear blocks of the source buffer after they have sourced the read operation in anticipation of future operations on the source buffer. Quite often, the source blocks are cleared (e.g. written with a background color) after the read operation has completed. This two-step sequential process of reading followed by source clearing is inefficient. Thus, there exists a need for a system and method capable of performing a read with source clear operation with increased efficiency relative to prior systems and methods.
SUMMARY OF THE INVENTION
In one set of embodiments, an interface device may be configured according to the principles disclosed herein to control accesses to an array of memory devices so that read accesses may be performed in parallel with source-clear operations. Each memory device may include a level-one cache, a level-two cache and a storage cell array (e.g. an array of DRAM cells). The interface device may comprise a memory control processor, a data request processor and a block cleansing unit.
The memory control processor may be configured to control fetch operations from the storage cell arrays to the level-two caches and from the level-two caches to the level-one caches, and also to control write back operations from the level-one caches to the level-two caches. The level-two caches may be configured according to a write-through policy, i.e. data written to a level-two cache may be automatically written through to the corresponding storage cell array. The data request processor may be configured to write data items to a level-one cache in response to a write request, and to control a read access from a level-one cache in response to read requests.
The block cleansing unit couples to an array of status tags which are associated with blocks in the level-one caches. Each status tag include a mode indicator and a dirty tag associated with a level-one cache block. The dirty tags may have a dual interpretation. In a normal writeback mode, bits of a dirty tag indicate which data items in the corresponding level-one cache block have been written to. In a read clear mode, bits of a dirty tag indicate which data items in the corresponding level-one cache block have been read from (and thus require a source clear operation). The mode indicator determines the mode of interpretation for the corresponding dirty tag.
The block cleansing unit may examine the dirty tags of the status array and their corresponding mode indicators to detect level-one cache blocks that have been written to or read from. If the dirty tag of a level-one cache block indicates that it has been written to (i.e. one or more dirty tag bits are set) and the mode indicator is set to the normal writeback mode, the block cleansing unit may command the transfer of one or more data values from the level-one cache block to a corresponding one of the level-two caches. If the dirty tag of a level-one cache block indicates that it has been read from (i.e. one or more of the dirty tag bits are set) and the mode indicator is set to read-clear mode, the block cleansing unit may command a color fill transfer operation from the level-one cache that contains the level-one cache block to a corresponding level-two cache. In the color fill writeback operation, one or more data values in a color fill block of the level-one cache are transferred to the level-two cache. The color fill block may be programmed at some time prior to its use (e.g. at system initialization time, at the beginning of a frame or seqeunce of frames) to contain any desired background color or background pattern. The one or more data values transferred from level-one to level-two (in either normal writeback mode or read clear mode) may be determined by the dirty tag bits which are set.
In response to a read clear request (i.e. a read request that includes a read clear indication), the data request processor may control the transfer of data from a level-one cache block to an output buffer, and set one or more bits of the corresponding dirty tag to a first state and set the mode indicator associated with the first dirty tag to a read clear state. The data transferred to the output buffer may be used to generate a displayable image. For example, such data may comprise samples which may be filtered to determine pixels in a video frame.
In response to a write request, the data request processor may control write one or data items to a block of the level-one cache, and set the one or more bits of the corresponding dirty tag to the first state and set the associated mode indicator to the normal writeback state.
Each memory device may include a separate read bus and write bus between the level one cache and level two caches. This allows write back operations from level one to level two to occur simultaneously with block fetches from level two to level one. In particular, the source-clear operations (i.e. the color fill transfers) invoked by the block cleansing unit may be performed in parallel (i.e. simultaneously) with block fetch operations performed by the memory control processor.
The interface device may be incorporated as part of a graphics system which generates a stream of video pixels in response to received graphics data. The array of memory devices may form a frame buffer for the storage of the video pixels prior to output to a display device. The memory device array may also serve for the temporary storage of samples which are then filter to generate the video pixels.
REFERENCES:
patent: 5544306 (1996-08-01), Deering et al.
patent: 5757375 (1998-05-01), Kawase
patent: 5959639 (1999-09-01), Wada
patent: 6437789 (2002-08-01), Tidwell et al.
patent: 6591347 (2003-07-01), Tischler et al.
“OpenGL Reference Manual,” © 1992 pp. 74-75, 89-92, 101-107 and 251-256.
Kubalska Ewa M.
Lavelle Michael G.
Tang Yan Y.
Brightwell Mark K.
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Nguyen Hau
Sun Microsystems Inc.
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