Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-25
2004-07-20
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06766505
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of programmable integrated circuits and in particular, to a techniques and circuitry for more rapidly configuring programmable integrated circuits.
Integrated circuits are important building blocks of the modern age. Technology continues to evolve and integrated circuits continue to provide improved functionality. As integrated circuits improve, so do the electronics systems that are built using integrated circuits. There are many types of integrated circuit such as memories, microprocessors, application specific integrated circuits (ASICs), and programmable logic. Programmable logic integrated circuits such as PALs, PLDs, FPGAs, LCAs, and others are becoming more complex and continually evolving to provide more user-programmable features on a single integrated circuit. Modem programmable logic integrated circuits incorporate programmable logic including logic gates, products terms, or look-up tables. Programmable logic integrated circuits also included embedded user-programmable memory or RAM.
Despite the success of programmable logic, there is a continuing desire to provide greater functionality in a programmable logic integrated circuit, but at the same time, provide greater performance. As programmable logic becomes more highly integrated, more logical functions are provided, and therefore, more configuration bits are required to program or configure the functionality. More configuration bits leads to longer configuration or programming times, which is undesirable. For example, this may cause relatively long system start-up times because programmable logic having volatile memory cells such as static RAM cells need to be reprogrammed upon power up.
Therefore, there is a need to provide techniques and circuitry for more rapidly configuration programmable integrated circuit.
SUMMARY OF THE INVENTION
The invention provides techniques and circuitry for more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel, and this data is also handled internally in parallel. The configuration data will be stored in a data register. This data register has two or more register chains. In one implementation, there is one register chain for each of the data inputs. The configuration data is input into the two of more chains of the data register in parallel. Circuitry is also provided to handle redundancy.
In an embodiment, the invention is a programmable logic integrated circuit. The integrated circuit has n configuration bit inputs to input in parallel, n bits at a time, k configuration bits. The variable n is an integer greater than 1, k is greater than n, and k is a number of configuration bits in a frame for configuring the programmable logic of the programmable logic integrated circuit. The integrated circuit also has a data register to store at least the k configuration bits. The data register has n inputs, each inputting to one of n serial chains of registers of length m, where (m*n) is less than or equal to k.
The data register is divided into n chain and each of n configuration bit inputs is connected to input configuration bits to one of the n chains. In a specific embodiment, n is 8. The registers may be implemented or interchanged with latches, flip-flops, or other circuitry to implement the equivalent functionality.
Furthermore, the programmable logic integrated circuit may include a cyclic redundancy check (CRC) circuit, which is connected to a first the n configuration bit inputs. The cyclic redundancy check circuit performs a cyclic redundancy check on the configuration bits transferred through the first of the n configuration bit inputs. The circuitry will generate an error signal in the case of an error.
A stage X of the data register may include a first register and a second register. In stage X, a first multiplexer has inputs connected to an output of a first register of a stage X−1 of the data register and an output of a second register of stage X−1 of the data register, and an output connected to an input of the first register. A second multiplexer has inputs connected to the output of a second register of a stage X−1 of the data register and an output of the second register of a stage X of the data register, and an output connected to an input of the second register.
Stage X of the data register may further include a third multiplexer having inputs connected to the outputs of the first and second registers of stage X−1 and to the outputs of the first and second registers of stage X, and an output connected to inputs of a stage X+1 of the data register.
In a further embodiment, the invention is a method of configuring a programmable logic integrated circuit. A number of configuration bits are input into the programmable logic integrated circuit in parallel using a first input and a second input. The configuration bits provided by the first input are loaded starting at a first register of a first chain a data register. The first chain includes registers connected together in a serial fashion. The configuration bits provided by the second input are loaded starting at a first register of a second chain the data register. The second chain also includes registers connected together in a serial fashion
In another embodiment, the invention is a programmable integrated circuit including
a first data input and a second data input. A data register holds configuration bits used to configure the programmable integrated circuit. The data register includes a first chain with a number of registers connected in a serial fashion and a second chain with a number of registers connected in serial fashion. The first register of the first chain is connected to the first data input. The first chain has the same number of registers as the second chain. A number of static RAM cells may be configured using the configuration bits.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
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Chong Yan
Huang Joseph
Kim In Whan
Nguyen Khai
Pan Philip
Altera Corporation
Levin Naum B
Siek Vuthe
Townsend and Townsend / and Crew LLP
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